Advanced PLL Interface

The following sections describe the advanced PLL and how to use it. Refer to the Package/Interface Support Matrix to find out if your FPGA supports the advanced PLL.

Note: At startup, Efinix recommends that you hold the PLL in reset until the PLL's reference clock source is stable.

Similarly, Efinix recommends resetting all cascaded PLLs at startup. Hold the first PLL in reset until the PLL's reference clock source is stable. Hold the cascaded PLLs in reset until the previous PLL is locked.

Cascaded PLLs do not need a 50% duty cycle on the reference clock. However, the clock needs to meet the PLL minimum pulse width as specified in the data sheet.