Using the PLL Block

Trion FPGAs (except the T4 and T8 in BGA49 and BGA81 packages) have an advanced PLL. This PLL is referenced as PLL_V2 in the Python API. This block lets you configure the reference clock, feedback options, frequency, and output clocks for the PLL. You can set up the PLL using the PLL Clock Calculator or manually using the Block Editor.

  • In the PLL's Properties tab, you specify general settings such as the instance name, PLL resource, clock source, and external clock.
  • Click the Automated Clock Calculation button to open the PLL Clock Calculator.
  • Click the Manual Configuration tab to configure the PLL manually.
Note: For FPGAs with DDR, PLL_BR0 is the clock resource for the DDR block. If you are using the DDR block with PLL_BR0, the PLL's CLKOUT0 can only drive the DDR PHY. You can use the PLL's CLKOUT1 and CLKOUT2 while the DDR is using CLKOUT0.

Reference Clock Settings

The PLL has four possible reference clocks. Two of the clocks can come from the FPGA core, and two can come from off chip. You select the clocks using the Clock Source drop-down box:

  • core—The PLL reference clock comes from the FPGA core.
  • external—Enables clock 0 and clock 1. The PLL reference clock comes from an external pin. The GUI displays the resource(s) that can be the reference clock.
    Note: In this mode, a GPIO or LVDS RX block with a pll_clkin connection type must generate the reference clock(s). The software displays which resource you need to use (and the instance name if you have created it).
    1. Add a GPIO block.
    2. Enter the instance name.
    3. Choose input as the mode.
    4. Choose pll_clkin as the connection type.
    5. In the Resource Assigner, assign it to the resource shown in the PLL's Properties tab.
  • dynamic—Enables all four clocks; requires a clock selector bus to choose the clock dynamically. The GUI displays the resource(s) that can be the reference clock.