SPI Active

Figure 1. SPI Active Mode (x1) Timing Sequence
The JTAG pins must be inactive during SPI active configuration.
Table 1. Active Mode Timing Parameters
Symbol Parameter Frequency Min Typ Max Units
fMAX_M Active mode configuration clock frequency.1 DIV4 14 20 26 MHz
DIV8 7 10 13 MHz
tSU Setup time. Test condition at 3.3 V I/O standard and 0 pF output loading. – 7.5 – – ns
tH Hold time. Test condition at 3.3 V I/O standard and 0 pF output loading. – 1 – – ns
tDMIN Minimum time between deassertion of CRESET_N to first valid configuration data. – 1.2 – – μs
Note: Refer to Power Up Sequence for details on the power-up requirements.
1 For parallel daisy chain x2 and x4, the active configuration clock frequency, fMAX_M, must be set to DIV4.