About the LVDS Interface

The LVDS hard IP transmitters and receivers operate independently.
  • LVDS TX consists of LVDS transmitter and serializer logic.
  • LVDS RX consists of LVDS receiver, on-die termination, and de-serializer logic.

The Trion has one PLL for use with the LVDS receiver.

Trion® FPGAs have one or more PLLs for use with the LVDS receiver, depending on which FPGA you use.

Note: You can use the LVDS TX and LVDS RX channels as 3.3 V single-ended GPIO pins, which support a weak pull-up but do not support a Schmitt trigger or variable drive strength. When using LVDS as GPIO, make sure to leave at least 2 pairs of unassigned LVDS pins between any GPIO and LVDS pins. This rule applies for pins on each side of the device (top, bottom, left, right). This separation reduces noise. The Efinity software issues an error if you do not leave this separation.

You can use the LVDS TX and LVDS RX channels as single-ended GPIO pins, see About the General-Purpose I/O Logic and Buffer. The voltage supported depends on the FPGA.

Note: When LVDS resources are used for both LVDS and GPIO within the same bank, they must be separated by 2 unused pairs of LVDS pins to avoid any unwanted interference. The Efinity software issues an error if you do not leave this separation. Refer to Table 1.

The LVDS hard IP has these features:

  • Dedicated LVDS TX and RX channels (the number of channels depends on the FPGA and package)
  • Up to 800 Mbps for LVDS data transmit or receive
  • Up to 600 or 800 Mbps for LVDS data transmit or receive (depending on the FPGA and package)
  • Supports serialization and deserialization factors: 8:1, 7:1, 6:1, 5:1, 4:1, 3:1, and 2:1
  • Ability to disable serialization and deserialization
  • Source synchronous clock output edge-aligned with data for LVDS transmitter and receiver
  • 100 Ω on-die termination resistor for the LVDS receiver
Note: The LVDS RX supports the sub-lvds, slvs, HiVcm, RSDS and 3.3 V LVPECL differential I/O standards with a transfer rate of up to 800 Mbps.