Interface Blocks

Trion® FPGAs support a variety of interface blocks. The available blocks differ depending on which FPGA you target and the package. You need to assign a resource for every block you use.

The following table describes the interface blocks supported in the Efinity® software.

Note: New package support is often added in patches. Refer to the Efinity Release Notes in the Support Center for the latest patch support.
Table 1. Trion Interface Block Support by Package
Interface T4 T8 T13 T20 T35 T55 T85 T120
GPIO All All All All All All All All
GPIO bus All All All All All All All All
I/O bank All All All All All All All All
JTAG User TAP1 F81 F81, Q144 All All All All All All
LVDS – Q144 All Q100, Q144, F169, F256, F324, F400 All All All All
MIPI – – F169 W80, F169, F324 F324 All F324, F576 F324, F576
DDR – – – F324, F400 F324, F400 All All All
Simple PLL (V1) All F49, F81 – – – – – –
Advanced PLL (V2) – Q144 All All All All All All
Oscillator All F49, F81 – – – – – –
SPI Flash – – Q100 Q100 – – – –

All interface blocks have an instance name that must be a unique identifier. When you add a new block, the Interface Designer gives the block a unique default name, which you can change.

Note: After you re-name the block, press Enter or click Save to save the name.

Pin names are the top-level ports of the design implemented in the core that connect to the interface block. These names must be legal Verilog HDL or VHDL identifiers.

1 The T4 and T8 in the F49 package do not support the JTAG User TAP because this package does not have the dedicated JTAG pins (TDI, TDO, TCK, TMS).