MIPI RX

The MIPI RX is a receiver interface that translates HSSI signals from the board to video data in the Trion® core. Five high-speed differential pin pairs (one clock, four data), each of which represent a lane, connect to the board. Control, video, and status signals connect from the MIPI interface to the core.

Figure 1. MIPI RX x4 Block Diagram

The control signals determine the clocking, how many transceiver lanes are used, and how many virtual channels are enabled. All control signals are required except the two reset signals. The reset signals are optional, however, you must use both signals or neither.

The video signals send the decoded video data to the core. All video signals must fully support the MIPI standard.

The status signals provide optional status and error information about the MIPI RX interface operation.

Figure 2. MIPI RX Interface Block Diagram
Table 1. MIPI RX Control Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Notes
CAL_CLK Input N/A Used for D-PHY calibration; must be between 80 and 120 MHz.
PIXEL_CLK Input N/A Clock used for transferring data to the core from the MIPI RX block. The frequency based on the number of lanes and video format.
Refer to Understanding the RX and TX Pixel Clock.
DPHY_RSTN Input N/A (Optional) Reset for the D-PHY logic, active low. Must be used if RSTN is used.
See MIPI Reset Timing.
RSTN Input N/A (Optional) Reset for the CSI-2 controller logic, active low. Must be used if DPHY_RSTN is used.
See MIPI Reset Timing.
VC_ENA[3:0] Input PIXEL_CLK Enables different VC channels by setting their index high.
LANES[1:0] Input PIXEL_CLK Determines the number of lanes enabled:
00: lane 0
01: lanes 0 and 1
11: all lanes
Can only be set during reset.
Table 2. MIPI RX Video Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Notes
VSYNC[3:0] Output PIXEL_CLK Vsync bus. High if vsync is active for this VC.
HSYNC[3:0] Output PIXEL_CLK Hsync bus. High if hsync is active for this VC
VALID Output PIXEL_CLK Valid signal.
CNT[3:0] Output PIXEL_CLK Number of valid pixels contained in the pixel data.
DATA[63:0] Output PIXEL_CLK Video data, format depends on data type. New data every pixel clock.
TYPE[5:0] Output PIXEL_CLK Video data type.
VC[1:0] Output PIXEL_CLK Virtual channel (VC).
Table 3. MIPI RX Status Signals (Interface to FPGA Fabric)
Signal Direction Signal Interface Clock Domain Notes
ERROR[17:0] Output IN PIXEL_CLK Error bus register. Refer to Table 4 for details.
CLEAR Input OUT PIXEL_CLK Reset the error registers.
ULPS_CLK Output IN PIXEL_CLK High when the clock lane is in the Ultra-Low-Power State (ULPS).
ULPS[3:0] Output IN PIXEL_CLK High when the lane is in the ULPS mode.
Table 4. MIPI RX Error Signals (ERROR[17:0])
Bit Name Description
0 ERR_ESC Escape Entry Error. Asserted when an unrecognized escape entry command is received.
1 CRC_ERROR_VC0 CRC Error VC0. Set to 1 when a checksum error occurs.
2 CRC_ERROR_VC1 CRC Error VC1. Set to 1 when a checksum error occurs.
3 CRC_ERROR_VC2 CRC Error VC2. Set to 1 when a checksum error occurs.
4 CRC_ERROR_VC3 CRC Error VC3. Set to 1 when a checksum error occurs.
5 HS_RX_TIMEOUT_ERR HS RX Timeout Error. The protocol should time out when no EoT is received within a certain period in HS RX mode.
6 ECC_1BIT_ERROR ECC Single Bit Error. Set to 1 when there is a single bit error.
7 ECC_2BIT_ERROR ECC 2 Bit Error. Set to 1 if there is a 2 bit error in the packet.
8 ECCBIT_ERROR ECC Error. Asserted when an error exists in the ECC.
9 ECC_NO_ERROR ECC No Error. Asserted when an ECC is computed with a result zero. This bit is high when the receiver is receiving data correctly.
10 FRAME_SYNC_ERROR Frame Sync Error. Asserted when a frame end is not paired with a frame start on the same virtual channel.
11 INVLD_PKT_LEN Invalid Packet Length. Set to 1 if there is an invalid packet length.
12 INVLD_VC Invalid VC ID. Set to 1 if there is an invalid CSI VC ID.
13 INVALID_DATA_TYPE Invalid Data Type. Set to 1 if the received data is invalid.
14 ERR_FRAME Error In Frame. Asserted when VSYNC END received when CRC error is present in the data packet.
15 CONTROL_ERR Control Error. Asserted when an incorrect line state sequence is detected.
16 SOT_ERR Start-of-Transmission (SoT) Error. Corrupted high-speed SoT leader sequence while proper synchronization can still be achieved.
17 SOT_SYNC_ERR SoT Synchronization Error. Corrupted high-speed SoT leader sequence while proper synchronization cannot be expected.
Note: If error report is all logic low, there is an EOT or a contention error. Check the physical connection of MIPI lanes or adjust the EXIT and TRAIL parameters according to the MIPI Utility.
Table 5. MIPI RX Pads
Pad Direction Description
RXDP[4:0] Input MIPI transceiver P pads.
RXDN[4:0] Input MIPI transceiver N pads.
Table 6. MIPI RX Settings in Efinity® Interface Designer
Tab Parameter Choices Notes
Control DPHY Calibration Clock Pin Name User defined
Invert DPHY Calibration Clock On or Off
Pixel Clock Pin Name User defined
Invert Pixel Clock On or Off
Status Enable Status On or Off Indicate whether you want to use the status pins.
Lane Mapping RXD0, RXD1, RXD2, RXD3, RXD4 clk, data0, data1, data2, or data3 Map the physical lane to a clock or data lane.
Swap P&N Pin On or Off Reverse the P and N pins for the physical lane.
Timing Calibration Clock Freq (MHz) User defined Specify a number between 80 and 120 MHz.
Clock Timer (TCLK-SETTLE) 40 - 2,590 ns Changes the MIPI receiver timing parameters per the DPHY specification. Refer to D-PHY Timing Parameters.
Data Timer (THS-SETTLE) 40 - 2,590 ns Changes the MIPI receiver timing parameters per the DPHY specification. Refer to D-PHY Timing Parameters.