Complex I/O Buffer

T8 (Q144 only), T13 T20KGD, T20, T35, T55, T85, and T120 FPGAs have a complex I/O interface with logic and a buffer.

Figure 1. I/O Interface Block

Note: LVDS as GPIO do not have double data I/O (DDIO).

Table 1. GPIO Signals (Interface to FPGA Fabric)
Signal	Direction	Description
I[1:0]	Output	Input data from the GPIO pad to the core fabric. I[0] is the normal input to the core. In DDIO mode, I[0] is the data captured on the positive clock edge (HI pin name in the Interface Designer) and I[1] is the data captured on the negative clock edge (LO pin name in the Interface Designer).
ALT	Output	Alternative input connection (in the Interface Designer, Register Option is none). Alternative connections are GCLK, GCTRL, PLL_CLKIN, and MIPI_CLKIN.¹
O[1:0]	Input	Output data to GPIO pad from the core fabric. O[0] is the normal output from the core. In DDIO mode, O[0] is the data output on the positive clock edge (HI pin name in the Interface Designer) and O[1] is the data output on the negative clock edge (LO pin name in the Interface Designer).
OE	Input	Output enable from core fabric to the I/O block. Can be registered.
OUTCLK	Input	Core clock that controls the output and OE registers. This clock is not visible in the user netlist unless you instantiate an EFX_GPIO_V2 primitive.
INCLK	Input	Core clock that controls the input registers. This clock is not visible in the user netlist unless you instantiate an EFX_GPIO_V2 primitive.

Table 2. GPIO Pads
Signal	Direction	Description
IO	Bidirectional	GPIO pad.

¹ MIPI_CLKIN is only available in packages that support MIPI.