Pinout Description

The following tables describe the pinouts for power, ground, configuration, and interfaces.

Table 1. General Pinouts
Function Group Direction Description
VCC Power – Core power supply.
VCCA_xx Power – PLL analog power supply. xx indicates location:
TL: Top left, TR: Top right, BR: bottom right
VCCIOxx Power – I/O pin power supply. xx indicates the bank location:
1A: Bank 1A, 3E: Bank 3E
4A: Bank 4A (only for 3.3 V) , 4B: Bank 4B (only for 3.3 V)
VCCIOxx_yy_zz Power – Power for I/O banks that are shorted together. xx, yy, and zz are the bank locations. For example:
VCCIO1B_1C shorts banks 1B and 1C
VCCIO3C_TR_BR shorts banks 3C, TR, and BR
GND Ground – Ground.
CLKn Alternate Input Global clock network input. n is the number. The number of inputs is package dependent.
CTRLn Alternate Input Global network input used for high fanout and global reset. n is the number. The number of inputs is package dependent.
PLLIN Alternate Input PLL reference clock resource. There are 5 PLL reference clock resource assignments. Assign the reference clock resource based on the PLL you are using.
MREFCLK Alternate Input MIPI TX PLL reference clock source.
GPIOx_n GPIO I/O General-purpose I/O for user function. User I/O pins are single-ended.
x: Indicates the bank (L or R)
n: Indicates the GPIO number.
GPIOx_n_yyy
GPIOx_n_yyy_zzz
GPIOx_zzzn
 GPIO
Multi-Function
 I/O Multi-function, general-purpose I/O. These pins are single ended. If these pins are not used for their alternate function, you can use them as user I/O pins.
x: Indicates the bank; left (L), right (R), or bottom (B).
n: Indicates the GPIO number.
yyy, yyy_zzz: Indicates the alternate function.
zzzn: Indicates LVDS TX or RX and number.
TXNn, TXPn
 LVDS I/O LVDS transmitter (TX). n: Indicates the number.
RXNn, RXPn LVDS I/O LVDS receiver (RX). n: Indicates the number.
CLKNn, CLKPn LVDS I/O Dedicated LVDS receiver clock input. n: Indicates the number.
RXNn_EXTFBn
RXPn_EXTFBn
 LVDS I/O LVDS PLL external feedback. n: Indicates the number.
REF_RES – – REF_RES is a reference resistor to generate constant current for LVDS TX. Connect a 12 kΩ resistor with a tolerance of ±1% to the REF_RES pin with respect to ground. If none of the pins in a bank are used for LVDS, leave this pin floating.
Table 2. Dedicated Configuration PinsThese pins cannot be used as general-purpose I/O after configuration.
All the pins are in internal weak pull-up during configuration except for TCK and TDO.
Pins Direction Description External Weak Pull- Up/Pull Down Requirement
CDONE I/O Configuration done status pin. CDONE is an open drain output; connect it to an external pull-up resistor to VCCIO. When CDONE = 1, the configuration is complete and the FPGA enters user mode. You can hold CDONE low and release it to synchronize the FPGAs entering user mode. Pull up
CRESET_N Input Active-low FPGA reset and re-configuration trigger.
Pulse CRESET_N low for a duration of tcreset_N before releasing CRESET_N from low to high to initiate FPGA re-configuration. This pin does not perform a system reset.
 Pull up
TCK Input JTAG test clock input (TCK). The rising edge loads signals applied at the TAP input pins (TMS and TDI). The falling edge clocks out signals through the TAP TDO pin. Pull up
TMS Input JTAG test mode select input (TMS). The I/O sequence on this input controls the test logic operation . The signal value typically changes on the falling edge of TCK. TMS has an internal weak pull-up; when it is not driven by an external source, the test logic perceives a logic 1. Pull up
TDI Input JTAG test data input (TDI). Data applied at this serial input is fed into the instruction register or into a test data register depending on the sequence previously applied at TMS. Typically, the signal applied at TDI changes state following the falling edge of TCK while the registers shift in the value received on the rising edge. Like TMS, TDI has an internal weak pull-up; when it is not driven from an external source, the test logic perceives a logic 1. Pull up
TDO Output JTAG test data output (TDO). This serial output from the test logic is fed from the instruction register or a test data register depending on the sequence previously applied at TMS. The shift out content is based on the issued instruction. The signal driven through TDO changes state following the falling edge of TCK. When data is not being shifted through the device, TDO is set to an inactive drive state (e.g., high-impedance). Pull up
Note: All dedicated configuration pins have Schmitt Trigger buffer. See Table 5 for the Schmitt Trigger buffer specifications.
Table 3. Dual-Purpose Configuration PinsIn user mode (after configuration), you can use these dual-purpose pins as general I/O.
Pins Direction Description Use External Weak Pull-Up
CBUS[2:0] Input Configuration bus width select. CBUS has an internal weak pull-up. However, recommends that you use an external pull-up accordingly. See Selecting the Configuration Mode in AN 006: Configuring Trion FPGAs. Pull up or pull down1
CBSEL[1:0] Input Multi-image configuration selection pin. This function is not applicable to single-image bitstream configuration or internal reconfiguration (remote update).
Connect CBSEL[1:0] to the external resistors for the image you want to use:
00 for image 1
01 for image 2
10 for image 3
11 for image 4
0: Connect to an external weak pull down.
1: Connect to an external weak pull up.
 Pull up or pull down 2
CCK I/O
Passive SPI input configuration clock or active SPI output configuration clock (active low). Includes an internal weak pull-up.
 Optional3
CDIn I/O n is a number from 0 to 31 depending on the SPI configuration.
0: Passive serial data input or active serial output.
1: Passive serial data output or active serial input.
n: Parallel I/O.
In multi-bit daisy chain connection, the CDI (31:0) connects to the data bus in parallel.
 Optional3
CSI Input Chip select.
0: The FPGA is not selected or enabled and will not be configured.
1: Selects the FPGA for all configuration modes. CSI must remain high throughout all configuration modes.
 Pull up
CSO Output Chip select output. Selects the next device for cascading configuration. N/A
NSTATUS Output Status (active low).
Indicates a configuration error. When the FPGA drives this pin low, it indicates either a device mismatch or a failed bitstream CRC check.
N/A
SS_N Input
SPI configuration mode select. The FPGA senses the value of SS_N when it comes out of reset (i.e., CRESET_N transitions from low to high).
0: SPI Passive mode; connect to external weak pull down.
1: SPI Active mode; connect to external weak pull up.
In active configuration mode, SS_N is an active-low chip select to the flash device (CDI0 - CDI3).
 Optional3
TEST_N Input Active-low test mode enable signal. Set to 1 to disable test mode.
During all configuration modes, rely on the external weak pull-up or drive this pin high.
Pull up
Table 4. MIPI Pinouts (Dedicated)n Indicates the number. L indicates the lane
Function Group Direction Description
VCC25A_MIPI0
VCC25A_MIPI1
 Power – MIPI 2.5 V analog power supply.
VCC12A_MIPI0_TX
VCC12A_MIPI1_TX
 Power – MIPI 1.2 V TX analog power supply.
VCC12A_MIPI0_RX
VCC12A_MIPI1_RX
 Power – MIPI 1.2 V RX analog power supply.
GNDA_MIPI Ground – Ground for MIPI analog power supply.
MIPIn_TXDPL
MIPIn_TXDNL
 MIPI I/O MIPI differential transmit data lane.
MIPIn_RXDPL
MIPIn_RXDNL
 MIPI I/O MIPI differential receive data lane.
MREFCLK Clock Input MIPI PLL reference clock source.
Table 5. DDR Pinouts (Dedicated)n indicates the number.
Function Direction Description
VCCIO_DDR – DDR power supply.
DDR_A[n] Output Address signals to the memories.
DDR_BA[n] Output Bank signals to the memories.
DDR_CAS_N Output Active-low column address strobe signal to the memories.
DDR_CKE Output Active-high clock enable signals to the memories.
DDR_CK
DDR_CK_N
 Output Differential clock output pins to the memories.
DDR_CS_N Output Active-low chip select signals to the memories.
DDR_DQ[n] I/O Data bus to/from the memories.
DDR_DM[n] Output Active-high data-mask signals to the memories.
DDR_DQS_N[n] I/O Differential data strobes to/from the memories.
DDR_DQS[n] I/O Differential data strobes to/from the memories.
DDR_ODT Output ODT signal to the memories.
DDR_RAS_N Output Active-low row address strobe signal to the memories.
DDR_RST_N Output Active-low reset signals to the memories.
DDR_WE_N Output Active-low write enable strobe signal to the memories.
DDR_VREF I/O Reference voltage.
DDR_ZQ I/O ZQ calibration pin.
Table 6. SPI Flash Memory Pin
Function Direction Description
SPI_CS_N Input Active-low internal SPI flash memory chip select. Available in QFP100F3 packages only.
1 Optional for x1 mode.
2 Not applicable to single-image or remote update.
3 Optional unless pull-up is required by external load.