Revision History

In Design Check topics, added message about excluded pins. (DOC-2739)

Added warning message for pll_rule_feedback_clock about 0 degree phases for feedback clocks. (DOC-2036)

Updated the MIPI D-PHY Block Editor parameter name for the D-PHY speed (bandwidth instead of frequency). (DOC-1706)

Removed Dynamic Enable Pin Name from Table 3. This feature is not available in Trion FPGAs. (PT-2355)

Correct link to table that describes which package supports the simple PLL. (DOC-1847)

Added reset recommendations for PLLs and cascaded PLLs. (DOC-1900)

Added topic on clocking interface blocks. (DOC-1412)

Added LVDS TX Static Mode Delay Setting. (DOC-1473)

Updated SPI flash block topic. (DOC-1503)

Enhanced LVDS TX block Output Load parameter notes.

Added support for QFP100F3 packages and SPI Flash Interface block. (DOC-1296)

Added note to use LVDS blocks from the same side to minimize skew. (DOC-1150)

Updated Advanced PLL Settings table descriptions. (DOC-945)

Updated PLL Interface Designer Settings - Manual Configuration Tab notes. (DOC-1019)

Removed PLL_EXTFB. (DOC-849)

Updated important note for LVDS as GPIO and add LVDS resources assigment table. (DOC-886)

Added topics on Package Planner.

Updated Advanced PLL LOCKED signal description. (DOC-763)

Updated Package/Interface Support Matrix (DOC-791).

Clarified settings for creating LVDS TX and RX interfaces (DOC-791).

Added T20 QFP144 to the Interface/Package Combinations table; W80 does not have LVDS. (DOC-791)

Updated JTAG mode connection diagram. (DOC-546)

When using a serialization of 3, the LVDS TX requires a 45° phase shift. (DOC-688)

Renamed simple PLL as V1 and renamed advanced PLL as V2.

Added Parallel Clock Division parameter to the LVDS TX Interface Designer settings.

Updated Density parameter description and added 256Mb to choice to LPDDR2 in DDR Interface Designer Settings. (DOC-377)

Added LVDS TX and RX timing example for serialization width of 7. (DOC-359)

Updated REF_CLK description for clarity.

Added notes to Output Load parameter in LVDS TX Settings in Efinity® Interface Designer table.

Changed the name of the GPIO connection type from none to normal.

Some alternate connection types are available as inputs to the core.

Described how to use the PLL calculator for the simple PLL.

Updated the notes for Output Load parameter in LVDS TX Settings in Efinity Interface Designer. (DOC-309)

Updated PLL reference clock input note by asking reader to refer to PLL Timing and AC Characteristics. (DOC-336)

Removed OE and RST from LVDS block as they are not supported in software. (DOC-328)

Added floorplan diagram for T20 FPGAs in WLCSP80 package.

Added WLCSP80 package to the Package/Interface matrix.

Added supported features for GPIO and LVDS as GPIO.

Added a topic on using LVDS as GPIO.

Added note to LVDS RX interface block diagram.

Added note about using output divider value of 4 when the LVDS receiver speed is higher 600 Mbps.

Updated the LVDS RX and TX serilization and alternate function option descriptions.

Updated the maximum F_VCO for advanced PLL to 1,600 MHz.

You can use the PLL's CLKOUT1 and CLKOUT2 while the DDR is using CLKOUT0.

The DDR PLL reference clock must be driven by I/O pads.

Updated the DDR DRAM reset signal from RST_N to CFG_RST_N.

Corrected DDR DRAM block diagram by adding DDR_CK signal.

In MIPI RX and RTX interface description, updated maximum data pixels for RAW10 data type.

Removed all instances of DDR3U.

Added note to refer to AN 021 for boundary-scan testing information.

Removed Efinity Interface Designer JTAG User TAP Interface subsection and added note and link to Efinity® Software User Guide for more information about JTAG User TAP interface.

Added BGA400 package to interface matrix.

Added BGA400 interface diagram.

Added BGA400 I/O bank information.

Updated PLLCLK pin name to PLL_CLKIN.

Added PLL_EXTFB and MIPI_CLKIN as an alternative input in GPIO signals table for complex I/O buffer.

Updated Memory CAS Latency (CL) choices in Advanced Options tab - Memory Mode register settings subtab.

Updated Output Drive Strength choices for LPDDR2 in Advanced Options tab - Memory Mode register settings subtab.

Corrected Enable Target 1 parameter notes in AXI 0 and AXI 1 tabs.

Removed restriction on CLKOUT1 and CLKOUT2 when CLKIN is used to drive the DDR on CLKOUT0 in DDR DRAM PHY signals table.

Updated description of how to select double data I/O for GPIO blocks.

Added a note about restrictions when using PLL_BR0 with the DDR block.

Described the enhanced Resource Assigner.

Added new FPGA and package support.

Restructured the I/O bank information into a table.

Added information for T55, T85, and T120 FPGAs.

Added the DDR interface description.

Added DDIO information to GPIO section.

Published content in PDF as well as HTML Help.

Minor changes throughout.