Ports

Table 1. Triple Speed Ethernet MAC Core Port Interface
Port Name Direction Bus Width Clk Domain Description
Clock and Reset1
init_clk input 1 – Freq = 50MHz or below
init_rst_n input 1 Async Reset all Power-Up Handshake between Soft IP and the FPGA PHY.
tx_mac_aclk input 1 – See Table 1 for more details.
rx_mac_aclk output 1 –
mac_reset input 1 Async Active high system global reset.
proto_reset input 1 Async Active high protocol reset on TX and RX path.
MAC AXI ST Interface: TX
tx_axis_clk Input 1 – TX AXI ST Interface. See TX AXI ST Interface for more details.
tx_axis_mac_tdata input AXI_WIDTH tx_axis_clk
tx_axis_mac_tvalid input AXI_WIDTH/8 tx_axis_clk
tx_axis_mac_tlast input 1 tx_axis_clk
tx_axis_mac_tstrb input AXI_WIDTH/8 tx_axis_clk
tx_axis_mac_tuser input 1 tx_axis_clk
tx_axis_mac_tready output 1 tx_axis_clk
MAC AXI ST Interface: RX
rx_axis_clk input 1 – RX AXI ST Interface. See RX AXI ST Interface for more details.
rx_axis_mac_tdata output AXI_WIDTH rx_axis_clk
rx_axis_mac_tvalid output 1 rx_axis_clk
rx_axis_mac_tlast output 1 rx_axis_clk
rx_axis_mac_tstrb output AXI_WIDTH/8 rx_axis_clk
rx_axis_mac_tuser output 1 rx_axis_clk
rx_axis_mac_tready input 1 rx_axis_clk
GMII Interface
gm_tx_c output 1 – Provides timing reference for the transfer of gm_tx_ signals to the PHY.
Source from tx_mac_aclk.
gm_tx_d output GMII_WIDTH gm_tx_c GMII transmits data bus to PHY.
gm_tx_en output GMII_WIDTH/8 gm_tx_c Indicates valid data on the transmit data bus when asserted.
gm_tx_err output GMII_WIDTH/8 gm_tx_c Indicates to the PHY that the transmitted frame is invalid when asserted.
gm_rx_c input 1 – GMII receives clock sourced from the PHY.
gm_rx_d input GMII_WIDTH gm_rx_c GMII receives data bus from PHY.
gm_rx_dv input GMII_WIDTH/8 gm_rx_c Indicates valid data on the receive data bus when asserted.
Continue to assert this signal during frame reception, from the first preamble byte until the last byte of the CRC field is received.
gm_rx_err input GMII_WIDTH/8 gm_rx_c Indicates that the received frame contains errors when asserted.
RGMII Interface
rgmii_txc_HI output 1 – MSB of the RGMII transmit clock signal to the PHY.
Connect to Pin Name (HI) if the Double Data I/O option turns on for rgmii_txc bus in the Interface Designer. Set the clock pin name reference to 90° phase shift of tx_mac_aclk.
rgmii_txc_LO output 1 – LSB of RGMII transmit clock signal to the PHY.
Connect to Pin Name (LO) if the Double Data I/O option turns on for rgmii_txc bus in Interface Designer. Set the clock pin name reference to 90° phase shift of tx_mac_aclk.
rgmii_txd_HI output 4 tx_mac_aclk The 4 most significant bits (MSB) transmit data to the PHY.
Connect to Pin Name (HI) if the Double Data I/O option turns on for rgmii_txd bus in Interface Designer. Set the clock pin name reference to tx_mac_aclk.
rgmii_txd_LO output 4 tx_mac_aclk 4 least significant bit (LSB) of RGMII transmit data to the PHY.
Connect to Pin Name (LO) if the Double Data I/O option turns on for rgmii_txd bus in Interface Designer. Set the clock pin name reference to tx_mac_aclk.
rgmii_tx_ctl_HI output 1 tx_mac_aclk MSB of the transmit control signal to the PHY.
Connect to Pin Name (HI) if the Double Data I/O option turns on for rgmii_tx_ctl bus in Interface Designer. Set the clock pin name reference to tx_mac_aclk.
rgmii_tx_ctl_LO output 1 tx_mac_aclk LSB of transmit control signal to the PHY.
Connect to Pin Name (LO) if the Double Data I/O option turns on for rgmii_tx_ctl bus in Interface Designer. Set the clock pin name reference to tx_mac_aclk.
rgmii_rxc input 1 – RX clock from PHY. See Table 1 for frequency requirement.
rgmii_rxd_HI input 4 rgmii_rxc 4 MSB of RGMII receive data from the PHY.
Connect to Pin Name (HI) if the Double Data I/O option turns on for rgmii_rxd bus in Interface Designer. Set the clock pin name reference to rgmii_rxc.
rgmii_rxd_LO input 4 rgmii_rxc 4 LSB of RGMII receive data from the PHY.
Connect to Pin Name (LO) if the Double Data I/O option turns on for rgmii_rxd bus in the Interface Designer. Set the clock pin name reference to rgmii_rxc.
rgmii_rx_ctl_HI input 1 rgmii_rxc MSB of receive control signal from the PHY.
Connect to Pin Name (HI) if the Double Data I/O option turns on for rgmii_rx_ctl bus in Interface Designer. Set the clock pin name reference to rgmii_rxc.
rgmii_rx_ctl_LO input 1 rgmii_rxc LSB of receive control signal from the PHY.
Connect to Pin Name (LO) if the Double Data I/O option turns on for rgmii_rx_ctl bus in Interface Designer. Set the clock pin name reference to rgmii_rxc.
MII Interface
mii_txc input 1 – TX clock from PHY. See Table 1 for frequency requirement.
mii_txd output 4 mii_txc Transmit data to PHY.
mii_tx_dv output 1 mii_txc Transmit data valid.
mii_tx_err output 1 mii_txc An assertion indicates that the PHY that the frame was sent is invalid.
mii_rxc input 1 – RX clock from PHY. See Table 1 for frequency requirement.
mii_rxd input 4 mii_rxc Receive data from PHY.
mii_rx_dv input 1 mii_rxc Data valid. This signal indicates that the data on mii_rxd [3:0] is valid. The signal stays asserted during frame reception, from the first preamble byte until the last byte of the CRC field is received.
mii_rx_err input 1 mii_rxc Assert this signal to indicate that the received frame contains errors.
RMII Interface
rmii_clk_ref input 1 – See Table 1.
rmii_txd output 2 rmii_clk_ref Transmit data to the PHY.
rmii_tx_en output 1 rmii_clk_ref The assertion indicates that the data on the transmit data bus is valid.
rmii_rxd input 2 rmii_clk_ref Receive data from the PHY.
rmii_crs_dv input 1 rmii_clk_ref Receive valid data strobe.
rmii_rx_err input 1 rmii_clk_ref Assert this signal to indicate that the received frame contains errors.
APB Interface
s_paddr input 10 s_axi_aclk APB address.
s_pwdata input 32 s_axi_aclk APB write data.
s_pwrite input 1 s_axi_aclk APB write.
s_penable input 1 s_axi_aclk APB enable.
s_psel input 1 s_axi_aclk APB select.
s_prdata output 32 s_axi_aclk APB ready data.
s_pready output 1 s_axi_aclk APB ready.
s_perr output 1 s_axi_aclk APB slave error.
AXI-4 Lite Interface
s_axi_aclk input 1 – Register interface clock. SeeTable 1 for frequency requirement.
s_axi_awaddr input 10 s_axi_aclk AXI4-Lite write address bus.
s_axi_awvalid input 1 s_axi_aclk AXI4-Lite write address valid strobe.
s_axi_awready output 1 s_axi_aclk AXI4-Lite write address ready signal.
s_axi_wdata input 32 s_axi_aclk AXI4-Lite write data.
s_axi_wvalid input 1 s_axi_aclk AXI4-Lite write data valid strobe.
s_axi_wready output 1 s_axi_aclk AXI4-Lite write-ready signal.
s_axi_bresp output 2 s_axi_aclk AXI4-Lite write response.
s_axi_bvalid output 1 s_axi_aclk AXI4-Lite write response valid strobe.
s_axi_bready input 1 s_axi_aclk AXI4-Lite write response ready signal.
s_axi_araddr input 10 s_axi_aclk AXI4-Lite read address bus.
s_axi_arvalid input 1 s_axi_aclk AXI4-Lite read address valid strobe.
s_axi_arready output 1 s_axi_aclk AXI4-Lite read address ready signal.
s_axi_rresp output 2 s_axi_aclk AXI4-Lite read response.
s_axi_rdata output 32 s_axi_aclk AXI4-Lite read data.
s_axi_rvalid output 1 s_axi_aclk AXI4-Lite read data valid strobe.
s_axi_rready input 1 s_axi_aclk AXI4-Lite read data ready signal.
MDIO Interface
Mdo output 1 – Output data signal for communication with the PHY’s configuration and status registers.
MdoEn output 1 – Output data enable signal for the MDIO bidirectional bus.
In the Interface Designer, you have to create an INOUT tristate port, set Mdi as input, Mdo as output, and MdoEn as output enable.
Mdi input 1 – Input data signal for communication with the PHY’s configuration and status registers. Always set to high when not in use.
Mdc output 1 – MDIO clock management . Derived from s_axi_aclk based on supplied configuration data.
PHY Power Up Sequence
PMA_CMN_READY input 1 Async Output from PHY to indicate the readiness of PHY calibration
PMA_XCVR_PLLCLK_
EN_ACK
 input 1 Async Refer to Power Up Handshake with FPGA Transceiver.
PMA_XCVR_POWER_
STATE_ACK
 input 4 Async
PMA_RX_SIGNAL_
DETECT
 input 1 Async
PMA_XCVR_
PLLCLK_EN
 output 1 init_clk
PMA_XCVR_POWER_
STATE_REQ
 output 4 init_clk
phy_init_done output 1 Async
1 For details on Clock and Reset, refer to Clock Sources and 5.3 Reset Signals.