RX AXI ST Interface

At the RX AXI ST interface, rx_axis_mac_tvalid indicates the validity of the received data frame. rx_axis_mac_tdata carries the data decoded from the selected PHY Interface, while rx_axis_mac_tlast marks the final transfer of the frame. rx_axis_mac_tstrb indicates the positional validity of the data byte within the RX data frame, and rx_axis_mac_tuser signals that the received frame contains an error. See Erroneous RX Frame for further details.

When crc_fwd = 1, the rx_axis_mac_tdata port includes both the RX data frame and CRC octets. More details on CRC forwarding are provided in CRC Generation and Check and Figure 2.

If the AXI4-Stream interface bandwidth exceeds the PHY interface bandwidth (for example, when using a wider AXI data width or a faster AXI clock, the RX AXI stream may appear non-streaming even for valid frames. This occurs because the PHY provides data at a lower rate than the AXI interface can accept, resulting in intermittent valid cycles (rx_axis_mac_tvalid deasserted between data beats). This behavior is expected and does not indicate an error.