Resource Utilization

Note: The resources and performance values provided are based on some of the supported FPGAs. These values are just guidance and may change depending on the device resource utilization, design congestion, and user design.
Table 1. Resource Utilization
FPGA Mode LUTs FFs Memory Block DSP Block Efinity® Version1
T120F324 Cut-Through Mode (GMII) 2,131 / 112,128 (1.90%) 1,369 / 112,128 (1.22%) 12 / 1,056 (1.14%) 0 / 320 (0%) 2025.1
Store-Forward Mode (GMII) 2,568 / 112,128 (2.29%) 1782 / 112,128 (1.59%) 23 / 1,056 (2.18%) 0 / 320 (0%)
Ti375N1156 Cut-Through Mode (SGMII) 2,820 / 362,880 (0.77%) 1,515 / 362,880 (0.42%) 12 / 2,688 (0.45%) 0 / 1,344 (0%)
Store-Forward Mode (SGMII) 3,401 / 362,880 (0.94%) 2,025 / 362,880 (0.56%) 21 / 2,688 (0.78%) 0 / 1,344 (0%)
Tz75N676 Cut-Through Mode (SGMII) 2,820 / 129,600 (2.17%) 1,515 / 129,600 (1.17%) 12 / 960 (1.25%) 0 / 480 (0%)
Store-Forward Mode (SGMII) 3,401 / 129,600 (2.62%) 2,025 / 129,600 (1.56%) 21 / 960 (2.19%) 0 / 480 (0%)
Note: The resource utilization data is derived based on the default settings.
1 System Verilog 2005.