RGMII TX
For the RGMII interface, the Double Data I/O (DDIO) option must be
enabled for the transmission of clock, data, and control signals. Table 1 shows the recommended Block Editor settings for
rgmii_txc, rgmii_txd, and
rgmii_tx_ctl.
| Parameter | Setting | ||
|---|---|---|---|
| rgmii_txc | rgmii_txd [3:0] | rgmii_tx_ctl | |
| Mode | output | output | output |
| Register Option | register | register | register |
| Double Data I/O Option | resync | resync | resync |
| Clock Pin Name | – | – | – |
| Pin Name (HI) | rgmii_txc_HI | rgmii_txd_HI | rgmii_tx_ctl_HI |
| Pin Name (LO) | rgmii_txc_LO | rgmii_txd_LO | rgmii_tx_ctl_LO |
| Enable invert clock | Yes (Trion) No (Titanium) |
No | No |
| Output Clock Pin Name | clk_125m_90deg | clk_125m 1 | clk_125m |
In the Efinity Interface Designer, use the Create Block/ Create Bus menu to add these signals and configure them according to Table 1.
Figure 1 to Figure 3 illustrates the conversion from TX AXI ST to RGMII TX at different operating speeds with the recommended block editor settings in Table 1.
The RGMII specification requires a clock-to-data skew to ensure correct sampling. This skew can be introduced either by PCB trace routing or by enabling the RGMII Transmit Clock Delay option in the GUI. This option only applies to 10 Mbps and 100 Mbps operation.
At 1000 Mbps, the required clock-to-data skew is achived internally by selecting a clock
with a 90-degree phase shift (clk_125m_90deg) relative to the clock
used to drive the data signals as the output clock for the rgmii_txc
DDIO register. This configuration introduces an approximate 2 ns delay, aligning the
rgmii_txc edge at the center of the data valid window for the
transmitted RGMII data and control signals.
At 100 Mbps, the rgmii_txc_HI and rgmii_txc_LO signals
are generated by dividing tx_mac_aclk by 5. The transmitted data on
rgmii_txd_HI and rgmii_txd_LO are duplicated 5
times.
At 10 Mbps, the behavior is similar to 100 Mbps. The difference is that
rgmii_txc_HI and rgmii_txc_LO are generated by
dividing tx_mac_aclk by 50 instead of 5. The transmitted data on
rgmii_txd_HI and rgmii_txd_LO are duplicated 50
times instead of 5 times.
By default, the RGMII Transmit Clock Delay option is enabled, resulting in center-aligned operation.