Clock Sources

The Triple Speed Ethernet MAC core clock sources are shown in the following table.

Table 1. Clock Sources in the Triple Speed Ethernet MAC Core
Clock Name Frequency Description
tx_axis_clk Refer to Table 2. AXI4-Stream TX clock
rx_axis_clk Refer to Table 2. AXI4-Stream RX clock
s_axi_aclk Trion: ≤ 100 MHz
Others: ≤ 200 MHz
 Register access interface clock
init_clk ≤ 50 MHz To facilitate the power-up sequence of the FPGA transceiver PHY. Can be sourced from the PLL or CLKIN pin.
RGMII/ GMII/ SGMII
tx_mac_aclk 125 MHz RGMII/ GMII
Transmit path reference clock. Provides timing reference for the RGMII and GMII transmit interface.
2500 Mbps 156.25 MHz SGMII
  • Sourced from the FPGA transceiver forwarded clock to be source synchronous and eliminate additional clock PPM.
  • The same forwarded clock is also used to clock the 1G PCS in the FPGA transceiver.
1000 Mbps 62.5 MHz
100 Mbps 6.25 MHz
10 Mbps 0.625 MHz
gm_rx_c 125 MHz GMII
GMII receive clock sourced from the PHY.
2500 Mbps 156.25 MHz SGMII
  • Sourced from the FPGA Transceiver Forwarded Clock to be Source Synchronous and eliminate additional clock PPM.
  • The same Forwarded Clock is also used to clock the 1G PCS in the FPGA Transceiver.
1000 Mbps 62.5 MHz
100 Mbps 6.25 MHz
10 Mbps 0.625 MHz
rgmii_rxc 1000 Mbps 125 MHz RGMII receive clock sourced from the PHY.
100 Mbps 25 MHz
10 Mbps 2.5 MHz
RMII
rmii_clk_ref 50 MHz RMII reference clock.
MII
mii_txc 100 Mbps 25 MHz MII transmit clock sourced from the PHY.
10 Mbps 2.5 MHz
mii_rxc 100 Mbps 25 MHz MII receive clock sourced from the PHY.
10 Mbps 2.5 MHz

To prevent the AXI4-stream interface from limiting the performance, its clocks must meet the minimum frequency requirement listed in Table 2.

Table 2. Minimum Clock Frequency Requirement for tx_axis_clk and rx_axis_clk
Speed (Mbps) AXI4-Stream Data Width Min. Clock Frequency (MHz)
2500 8 312.5
16 156.25
32 78.125
1000 8 125
16 62.5
32 31.25
100 8 12.5
16 6.25
32 3.125
10 8 1.25
16 0.625
32 0.3125

Figure 1 shows the clock domains in the Triple Speed Ethernet MAC core.

Figure 1. Triple Speed Ethernet MAC Core Clock Domain
Note: In Cut Through mode, the AXI4-stream interface operates on the tx_mac_aclk and gm_rx_c clock domains. The tx_axis_clk andrx_axis_clk ports are not used in this mode and should be logic 0.