TX PHY Interface

At the PHY interface, Triple Speed Ethernet MAC core schedules transmit packets based on the following priority (highest to lowest):
  1. Pause mechanism triggered by a received pause frame.
  2. Request to transmit a pause frame (xon_gen/ xoff_gen)
  3. User data from TX AXI4-stream interface (tx_axis_mac_tvalid, tx_axis_mac_tlast, tx_axis_mac_tstrb, tx_axis_mac_tdata, and tx_axis_mac_tuser)

User data transfer from the tx_axis_mac signals interface always has the lowest priority. The Triple Speed Ethernet MAC core maps tx_axis_mac_tdata directly onto the transmit data bus of the selected PHY interface. Therefore, tx_axis_mac_tdata must begin with the Ethernet frame header, i.e., Destination address, source address, length / type, and optional VLAN tags. In the figures of this user guide, the header octets are shown as DATA, to focus on the conversion between the TX AXI ST interface and the selected PHY interface.

When a higher-priority event (pause mechanism or pause frame request) is asserted during an ongoing transfer, the Triple Speed Ethernet MAC core waits until the current frame transmission is completed before servicing the higher-priority request.

You can get details on the transmission priority handling in Priority Flow Control (Duplex Mode).