Reset Signals

The Triple Speed Ethernet MAC core has 3 reset signals. These signals are asynchronous. init_rst_n is active low, but mac_reset and proto_reset are active high.
  • mac_reset (Global Reset)
  • proto_reset (Protocol Reset)
  • init_rst_n (Initialization Reset)
During the FPGA power-up, intitalize mac_reset and proto_reset to 1, and init_rst_n to 0 to ensure the Triple Speed Ethernet MAC core is held in a known reset state.
  • mac_reset (Global Reset)
    • Resets all logic within the Triple Speed Ethernet MAC core, including control and status registers.
    • Only the power-up sequence module remains unaffected and operational.
  • proto_reset (Protocol Reset)
    • Resets both the TX and RX data paths, as well as the statistics counters.
    • Does not affect the power-up sequence module.
  • init_rst_n (Initialization Reset)
    • Used when pairing the Triple Speed Ethernet MAC core with an FPGA transceiver in SGMII mode.
    • Requires a free-running init_clk.
    • Upon IN_USER, deassert init_rst_n to start the power-up handshake with the FPGA ransceiver.
    • Must remain deasserted throughout normal operation.
    • Detailed power-up sequence is described in Power Up Handshake with FPGA Transceiver.
For synchronization reset, all three resets are asynchronous assertion or synchronous deassertion.
  • init_rst_n is synchronized internally to init_clk.
  • mac_reset and proto_reset are synchronized internally to their respective clock domains.
  • Each reset synchronizer introduces a 2 – 3 clock cycle latency upon deassertion.
Note: To ensure proper operation after reset deasssertion, you must delay data transmission by at least 3 clock cycles following the release of the reset signal. This delay allows sufficient time for the internal reset synchronizers to stabilize before any AXI4-Stream or PHY interface activity begins. Failure to observe this delay may result in undefined behavior or corrupted frame transmission during the startup process.

The Figure 1 shows the reset domains in the Triple Speed Ethernet MAC core.

Figure 1. Triple Speed Ethernet MAC Core Reset Domains