Example Design with FPGA Transceiver

Efinix provides the flollowing example design. The example design targets Titanium Ti375 N1156 Development Kit.

The example design illustrates the connectivity among the Triple Speed Ethernet MAC, FPGA 1G PCS, and the user’s logic, as shown in Figure 1. The user’s logic consists of 2 pattern generators and 2 checkers (denoted by efx_mac1gbe_exp_pat_gen and efx_mac1gbe_exp_checker modules respectively), APB modules (denoted by efx_mac1gbe_exp_apb_master and efx_mac1gbe_exp_apb_decoder), and a virtual I/O debugger.

The APB decoder decodes the APB address and routes the APB request to the corresponding APB slaves based on the address map in Table 1. The APB master contains a built-in RAM that captures the APB_PRDATA and the APB_PADDRESS of all APB Read commands. Ports ram_dout_d and ram_dout_a display the captured APB_PRDATA and the corresponding APB_PADDRESS.

Upon the assertion of IN_USER, the example design awaits the PLL to lock. The assertion of PLL_LOCK releases the resets in the Triple Speed Ethernet MAC core and the FPGA PCS. This is followed by the PHY power-up sequence handshake, resulting in the assertion of PHY_INIT_DONE. Upon the assertion of PHY_INIT_DONE, the APB modules become operational and are used to write the corresponding signal_ok register bit to 1, enabling the RX path, as depicted in the Titanium SGMII 1G and 2.5G User Guide.

After achieving synchronization status, the pattern generator starts transmitting data frames into the TX AXI ST interface of the Triple Speed Ethernet MAC core. Throughout the operation, the checker actively checks the RX path of the Triple Speed Ethernet MAC core for error frame and assertion of RX_AXI_TUSER. Test passes when ln_data_cnt and ln_frame_cnt are incremented with ln_err_cnt and ln_bad_frame_cnt remaining 0.