Control and Status Registers

As a general guideline, control registers should be programmed only when no data traffic is in progress.

Modifying configuration settings while the transmission or receiving traffic is active may result in unpredictable behavior or data corruption.

In practice, you are recommended to program control registers only when the datapath is disabled (by clearing tx_ena or rx_ena), with the following exceptions that may be configured at any time:
  • xon_gen
  • xoff_gen
  • pause_quant
  • tx_ena
  • rx_ena
Additionally, the following registers may be updated safely when the TX AXI ST interface is idle:
  • tx_addr_ins
  • tx_dst_addr_ins
  • dst_mac_addr
Table 1. Triple Speed Ethernet MAC Core Configuration Registers
Dword Offset Name R/W Description
0x00 VERSION R Indicates the version of the IP core.
Default: The default value is configurable through TSE MAC Version field in the IP Configuration window.
0x08 Command_Config R/W Command configuration settings. Refer to Table 2 for more details.
0x0C mac_addr [31:0] R/W Source MAC address.
Example: If the MAC address is set to 01-1B-43-17-7B-CD:
Write 0x43177BCD to register 0x0C
Write 0x0000011B to register 0x10
Default: The default value is configurable through MAC Source Address field in the IP Configuration window.
0x10 mac_addr [47:32] R/W
0x14 frm_length [15:0] R/W Indicates the maximum packet length.
Default: The default value is configurable through Maximum Transmission Unit Frame Length field in the IP Configuration window.
0x18 pause_quant [15:0] R/W Defines the pause quanta value inserted into the generated PAUSE frame triggered by xoff_gen.
Each PAUSE frame specifies a requested pause duration in units of pause quanta, where one quanta equals 512 bit times.
Example: If pause_quant is set to 8, the pause time equals 8 × 512-bit times.
Default: 0x0
0x5c tx_ipg_length [5:0] R/W Transmit interpacket gap value.
Default: The default value is configurable through the Programmable Inter Packet Gap field in the IP Configuration window.
Table 2. Command_Config Register Field Description
Bit Name R/W Description
0 tx_ena R/W Enables the transmission path.
Default: 1
1 rx_ena R/W Enables the receive path.
Default: 1
2 xon_gen R/W Pause frame generation.
Assert high to trigger a pause frame with 0 pause quanta to resume transmission. See Send Pause Frame at TX for more details.
Default: 0
3 Reserved
4 promis_en R/W Promiscuous mode. Assert high to disable MAC address filtering.
Default: 0
5 Reserved
6 crc_fwd R/W Assert high to forward the CRC value to the AXI4-Stream RX data rx_axis_mac_tdata.
Default: 0
7 Reserved
8 pause_ignore R/W Assert high to disable pause frame control.
Default: 0
9 tx_addr_ins R/W Assert high to insert the transmit packet’s source MAC address with the value in registers 0xC and 0x10.
Default: 0
10 -14 Reserved
15 loop_ena R/W Controls local PHY loopback at runtime. When loop_ena = 1, the MAC’s TX path is looped back to the RX path on the selected PHY interface.
Note: Local loopback support must be enabled in the IP Configuration window for this register bit to have any effect.
Default: 0
16 - 18 eth_speed [2:0] R/W Ethernet MAC transfer speed. For RGMII and RMII interface, correct configuration of the eth_speed setting is required to ensure proper clock generation and data sampling behavior. The setting must be configured before any traffic starts.
3’b100: 1000 Mbps
3’b010: 100 Mbps
3’b001: 10 Mbps
Default:
  • RGMII: 3’b100
  • RMII: 3'b010
Note: For MII, GMII, and SGMII modes, the eth_speed setting is not applicable and can be ignored.
19 - 21 Reserved
22 xoff_gen R/W Triggers the transmission of a pause frame. When set to 1, the MAC generates a pause frame using the quanta value specified in pause_quant (0x18).
The pause frame requests the link partner to pause transmission for pause_quant × 512 bit times.
See Send Pause Frame at TX for additional details on pause frame operation.
Default: 0
23 - 30 Reserved
31 cnt_reset R/W Assert high to reset all the statistic counter registers.
Default: 0
Note: For accurate counter values, this reset should only be performed when the Triple Speed Ethernet MAC core is idle (no active TX or RX operations). To ensure this, follow this sequence:
  1. Disable the datapath by clearing tx_ena and rx_ena.
  2. Assert cnt_reset to clear counters.
  3. Re-enable tx_ena and rx_ena.

Table 3. MDIO Configuration Registers
Dword Offset Name R/W Description
0x100 Bit 7:0 – Divider R/W To derive the Mdc clock frequency. The Mdc frequency = s_axi_aclk frequency / Divider.
Default: 0x64
Bit 8 - NoPre 0: Send the MDIO with preamble data.
1: Send the Mdio without preamble data.
Default: 0x0
0x104 Bit 0 - RdEn System Controlled Assert high to read the MDIO bus.
Default: 0x0
Bit 1 - WrEn Assert high to write to the MDIO bus.
Default: 0x0
0x108 Bit [4:0] – RegAddr R/W MDIO configuration register address.
Default: 0x0
Bit [7:5] – Reserved –
Bit [12:8] - PhyAddr 5-bit PHY address.
Default: 0x0
0x10c WrData [15:0] R/W MDIO write data.
Default: 0x0
0x110 RdData [15:0] R MDIO read data.
Default: 0x0
0x114 Bit 0 - LinkFailStatus R Fail to link with the PHY MDIO.
Default: 0x0
Bit 1 - BusyStatus PHY MDIO is busy.
Default: 0x0
Bit 2 - NvalidStatus Invalid Status (qualifier for the valid scan result).
Default: 0x0
Table 4. Receive Supplementary Registers
Dword Offset Name R/W Description
0x140 broadcast_filter_en R/W Controls the filtering of broadcast packets. When set to 1, all received packets with the broadcast destination MAC address (FF:FF:FF:FF:FF:FF) are discarded by the MAC.
When 0, broadcast packets are accepted. See Address Filtering and Broadcast Filtering at RX for more details.
Default: The default value is configurable through the Broadcast Filtering field in the IP Configuration window.
0x144 mac_addr_mask [31:0] R/W Specifies the MAC address mask for address filtering. Mask bits set to 1 are compared; bits set to 0 are ignored. Effective only when promis_en = 0. Refer to Address Filtering and Broadcast Filtering at RX for more details.
Default: 0x0
0x148 mac_addr_mask [47:32] R/W
Table 5. Transmit Supplementary Registers
Dword Offset Name R/W Description
0x180 tx_dst_addr_ins [0] R/W Assert high to insert the destination MAC address value in 0x184 and 0x188 to TX packet destination MAC address data bytes.
Default: 0x0
0x184 dst_mac_addr [31:0] R/W Destination MAC address.
Default: 0x0
0x188 dst_mac_addr [47:32] R/W

Table 6. Statistic Counter RegistersFor detailed information, refer to Statistic Reporting.
Dword Offset Name R/W Description
0x68 aFramesTransmittedOK [15:0] R Frames successfully transmitted, including pause frames.
Default: 0x0
0x6c aFramesReceivedOK [15:0] R Frames successfully received, excluding error frames. Includes pause frames.
Default: 0x0
0x70 aFrameCheckSequenceErrors [15:0] R Received frames with CRC errors.
Default: 0x0
0x80 aTxPAUSEMACCtrlFrames [15:0] R Pause frames transmitted.
Default: 0x0
0x84 aRxPAUSEMACCtrlFrames [15:0] R Pause frames received.
Default: 0x0
0x88 ifInErrors [15:0] R Erroneous RX frames and frames dropped due to broadcast or address filtering.
Default: 0x0
0x8c ifOutErrors [15:0] R Frames terminated as a bad frame on the TX channel.
Default: 0x0
0x98 aRxFrameMismatchedLength [15:0] R Received frames with mismatched physical length vs Length field.
Default: 0x0
0x9c aRxFilterFramesErrors [15:0] R Filtered packets due to address mismatch.
Default: 0x0
0xb4 etherStatsPkts [15:0] R Total frames received, including erroneous frames.
Default: 0x0
0xb8 etherStatsUndersizePkts [15:0] R Frames < 64 bytes (excludes error frames). Includes pause frames.
Default: 0x0
0xbc etherStatsOversizePkts [15:0] R Frames exceeding frm_length (excludes error frames).
Default: 0x0
0xc0 aFramesReceivedLen[15:0] R Length of received frame.
Default: 0x0
0xc4 aTxFifoOverflowFramesErrors[15:0] R Transmitted frames discarded due to TX FIFO overflow in Store Forward mode.
Default: 0x0
0xc8 aTxIncontinuityFramesErrors[15:0] R Transmitted frames with continuity errors.
Default: 0x0