Triple Speed Ethernet MAC Testbench

You can choose to generate the testbench when generating the Triple Speed Ethernet MAC core in the IP Manager Configuration window.

Note: You must include all .v and .sv files generated in the /testbench directory in your simulation.

Important: Efinix tested the testbench generated with the default parameter options only.

Efinix provides a ready-to-use Modelsim simulation script to help you quickly run the testbench. To execute the testbench, run the following command in a terminal application: vsim -c -do modelsim.do in a terminal application. You must have Modelsim installed on your computer to use this script.

Table 1. Testbench Files
Directory	Description
../Testbench	Contains the example design and testbench files.
../Testbench/aldec	Contains the encrypted simulation source code for Aldec.
../Testbench/modelsim	Contains the encrypted simulation source code for ModelSim.
../Testbench/ncsim	Contains the encrypted simulation source code for NCSim.
../Testbench/synopsys	Contains the encrypted simulation source code for Synopsys VCS.

The simulation testbench is set up in a loopback configuration, where the RGMII TX interface is directly connected to the RGMII RX interface. The test performs a Transmit MAC Packet Test, which verifies data integrity through transmit-receive loopback checking. Packet length is set to 100, Packet number is set to 1000, and Packet type is set to MAC pattern. You can configure the MAC speed, pattern generator type, and packet length in the testbench.

During simulation, the pattern generator sends packets and the checker verifies each received packet against the transmitted one.

If a packet matches correctly, the terminal prints a message similar to the following:

Each line indicates the simulation timestamp and the packet sequence number successfully received.

---- Configure TSE MAC IP register setting ---
9610000 - Correct MAC packet  0, received
18330000 - Correct MAC packet 1, received
27050000 - Correct MAC packet 2, received
35770000 - Correct MAC packet 3, received
44490000 - Correct MAC packet 4, received
53210000 - Correct MAC packet 5, received
61930000 - Correct MAC packet 6, received
70650000 - Correct MAC packet 7, received
79370000 - Correct MAC packet 8, received
88090000 - Correct MAC packet 9, received
96810000 - Correct MAC packet 10, received

Note: The testbench supports simulation for Triple Speed Ethernet MAC core only.

Note: Contact Efinix support at the Support Center to obtain the testbench for the Triple Speed Ethernet MAC core with FPGA PCS.