FIFO Mode

During FIFO mode, the Triple Speed Ethernet MAC core begins forwarding data as the frame is received but includes an internal FIFO to provide elasticity and safe clock domain crossing between the PHY and AXI clock domains.

This mode is required when the two clocks are asynchronous or operate at different frequencies.

Because data is written into and read out from FIFO, this mode introduces slightly higher latency compared to Cut Through mode.

The minimum RX FIFO depth depends on the PHY interface types and maximum frame size:
  • For SGMII Interface:
    • Without VLAN tag: RXFIFO Depth ≥ (14 Header Bytes + Maximum Payload Size) / 2
    • With VLAN tag: RXFIFO Depth ≥ (18 Header Bytes + Maximum Payload Size) / 2
  • For other interfaces (RGMII, MII, RMII, GMII)
    • Without VLAN tag: RXFIFO Depth ≥ (14 Header Bytes + Maximum Payload Size)
    • With VLAN tag: RXFIFO Depth ≥ (18 Header Bytes + Maximum Payload Size)