Power Up Handshake with FPGA Transceiver

Before starting the operation of the Triple Speed Ethernet MAC core, it needs to perform the power-up handshake with the FPGA transceiver.

The Triple Speed Ethernet MAC core includes a built-in power-up sequence module to handshake with the FPGA transceiver PHY. For the details on the power-up sequence in the FPGA transceiver, refer to the power-up sequence chapter of the Titanium SGMII 1G and 2.5G User Guide. Figure 1 shows the power-up handshake between the Triple Speed Ethernet MAC core and the FPGA transceiver.

The power-up sequence between the Triple Speed Ethernet MAC core and the FPGA transceiver PHY is clocked by init_clk. The assertion of phy_init_done indicates that the FPGA transceiver PHY is CDR-lock-to-data.

After the assertion of phy_init_done, you need to configure the FPGA transceiver PCS which uses the common APB interface. The APB interface is a common interface that is shared across all the 4 lanes within a Quad. You need to create APB modules to configure the PCS, based on the register mapping in the Titanium SGMII 1G and 2.5G User Guide. Figure 1 includes an illustration of APB Write to enable PCS RX in lane 2.

Figure 1. Power Up Handshake with the FPGA Transceiver PHY and PCS

Important: When the FPGA PHY is in reset, both mac_reset and init_rst_n need to be asserted too. Once the FPGA PHY recovers from the reset, the user needs to repeat the entire power-up handshake by de-asserting the init_rst_n to restart the power-up sequence.