Features
- Compliant with the IEEE Std. 802.3-2008 specification
- Supports VLAN frame and jumbo frame
- Supports 2500 Mbps, 1000 Mbps, 100 Mbps, and 10 Mbps in full-duplex mode
- 8-bit, 16-bit, and 32-bit AXI4-Stream user interface for packet transfer
- RGMII, MII, RMII, GMII, and SGMII PHY interfaces
- Optional internal FIFO buffers
- Programmable source and destination MAC addresses
- Programmable inter packet gap (IPG)
- Automatic padding on short frames
- Frame check sequence or CRC generation, checking, and forwarding
- Frame length check against user-defined MTU frame length for received packets
- Frame length check against the LENGTH field for received packets
- Supports broadcast, unicast, and multicast address filtering
- Supports pause frame flow control
- Management data I/O (MDIO) for PHY device management
- AXI4-Lite or APB user interface for MAC configuration register access
- Statistic reporting
- Includes an example design targeting:
- Trion T120 BGA324 Development Board
- Titanium Ti60 F225 Development Board
- Titanium Ti375 N1156 Development Board