Functional Description
The Triple Speed Ethernet MAC core does the following functions:
- Convert TX data packets from the AXI4-Stream to the PHY interface format.
- Decodes RX data packets from PHY interface format to AXI4-Stream.
- Generates the pause frame to be transmitted at the PHY interface.
- Identifies the pause frame and implements priority flow control through the
pause mechanism based on the decoded
PAUSE_QUANT. - Drops RX frames with a mismatched address through a bit-wise address filtering mask.
- Drops RX frames with broadcast address.
The Triple Speed Ethernet MAC core supports multiple industry-standard PHY interfaces. Table 1 provides an overview of the data bus widths and supported speeds. For detailed descriptions, refer to TX PHY Interface and RX PHY Interface.
| PHY Interface | Data Bus Width | Speed | |||
|---|---|---|---|---|---|
| 2.5 G | 1 G | 10/100/1000M | 10/100M | ||
| RGMII | 4-bit (Double data rate) | – |  |
|
|
| MII | 4-bit | – | – | – | |
| RMII | 2-bit | – | – | – | |
| GMII | 8-bit | – | |
– | – |
| SGMII | 16-bit | |
|
|
|