Revision History
| Date | Document Version | IP Version | Description |
|---|---|---|---|
| December 2025 | 6.1 | 7.1 | Removed note in Clock sources and Terminating Bad Tx Frames.
(DOC-2850) Added note in RGMII RX of RX PHY
Interface. Updated sub-topics in Terminating Bad TX Frames
and added new sub-topic Non-Streaming TX Data. Updated all
informations in the sub-topics and added new sub-topic Non-Streaming
RX Data Frame (SGMII) under Erroneous RX Frame. Updated
Send Pause Frame at TX of Priority Flow Comtrol (Duplex
Mode). Updated information in
aTxIncontinuityFramesErrors. Added note in Latency and
Example Design with External PHY. |
| December 2025 | 6.0 | 7.0 | New document release replacing the current document. (DOC-2710) |
| November 2024 | 5.2 | 6.3 | Updated IP Version in Revision History. (DOC-2185) |
| November 2024 | 5.1 | 6.4 |
Added Topaz in Device Support. (DOC-2176)
Added IP Version in Revision History. (DOC-2185)
|
| June 2024 | 5.0 | – | Updated Realigning the PHY Clock section. (DOC-1888) Removed
section Using the RGMII rgmii_rxc_edge and rgmii_txc_dly
Signals. Updated waveforms for Output Signals Waveform
with DDIO Enabled and RGMII Transmit Clock Delay Enabled
(Center-aligned) and Output Signals Waveform with DDIO Enabled and
RGMII Transmit Clock Delay Disabled (Edge-aligned). Added
new waveforms for Input Signals Waveform with DDIO Enabled and First
Sampling of RGMII Receive Data Using Falling Edge and Input Signals
Waveform with DDIO Enabled and First Sampling of RGMII Receive Data
Using Rising Edge. Added new data RGMII Transmit Clock
Delay and First Sampling of RGMII Receive Data in table Triple Speed
Ethernet MAC Core Parameters. Added a note for table Block
Editor Settings for rgmii_rx_ctl. Added important note in
Example Design and Testbench regarding using default parameters
options only. (DOC-1781) |
| December 2023 | 4.9 | – | Updated Titanium resource utilization. (DOC-1601) |
| June 2023 | 4.8 | – |
Added Device Support and release notes sections. (DOC-1234)
Updated rgmii_txc settings for example design and to run other
designs at 1000 Mbps.
|
| March 2023 | 4.7 | – | Added-in Normal Mode and Linked-Partner Mode sub-topic in Using
Wireshank topic. (DOC-1176) Updated program in Using the PHY RGMII
Clock-to-Data Delay (Trion Only). |
| February 2023 | 4.6 | – | Added Ti60 F225 Development Board example design support. (DOC-1152) |
| February 2023 | 4.5 | – | Added note about the resource and performance values in the resource and utilization table are for guidance only. |
| December 2022 | 4.4 | – | Updated example design. (DOC-1015) Added New in version
section. |
| October 2022 | 4.3 | – | Updated ports width and descriptions and added new ports. Updated
registers width and added new registers. Corrected
AXI4-Stream Data Width parameter option. Corrected
s_axi_wdata width. Updated example design directory and
file names. Added Description about realigning PHY clock
with top-module signals. |
| September 2022 | 4.2 | – | Added support for GMII, RMII, and MII PHY interfaces. Updated
core IP manager parameters. |
| April 2022 | 4.1 | – | Added note about RX packet error feature is not supported and user can ignore warnings on rgmii_rx_ctl_HI signal. (DOC-787) |
| December 2021 | 4.0 | – | Added example design in IP manager. Corrected PHY IC
description. Updated example design RISC-V SoC to Sapphire. Updated supported FIFO depth
to 16384. |
| November 2021 | 3.3 | – | Corrected Block Editor Settings for rgmii_rx_ctl and rgmii_tx_ctl signals. |
| October 2021 | 3.2 | – | Updated Block Editor Settings for rgmii_rx_ctl and rgmii_tx_ctl signals. (DOC-586) |
| October 2021 | 3.1 | – | Added note to state that the fMAX in Resource Utilization and Performance, and Example Design Implementation tables were based on default parameter settings. |
| June 2021 | 3.0 | – | Added missing rgmii_txc_LO interface description in the ports
table. Added parameters to set in Interface Designer DDIO
settings. Corrected Output Signals Waveform with DDIO
Enabled figure. Added note about including all
.v generated in testbench folder is
required for simulation. |
| December 2020 | 2.0 | – |
Updated user guide for Efinix® IP Manager
which includes added IP Manager topics, updated parameters, and user
guide structure.
|
| October 2020 | 1.2 | – | Corrected Bit 0 - axi4_st_mux_select of the example design
configuration registers description. Updated normal and link test
mode descriptions. Added aFramesReceivedLen[15:0] to
statistic counter register. (DOC-318) Added information
about adding delay to re-allign the PHY clock in the example design.
(DOC-318) Added settings to enable the hard DDIO blocks in
Interface Designer and waveforms after integrating the hard DDIO
blocks into the core. (DOC-318) |
| August 2020 | 1.1 | – | Updated the Using this Example with the RISC-V SDK topic. |
| July 2020 | 1.0 | – | Initial release. |