RGMII RX
For the RGMII interface, the Double Data I/O (DDIO) option must be
enabled for the receive data and control signals. Table 1
and Table 2 show the recommended Block Editor settings for
rgmii_rxd and rgmii_rx_ctl.
| Parameter | Setting | |
|---|---|---|
| rgmii_rxd [3:0] | rgmii_rx_ctl | |
| Mode | Input | Input |
| Register Option | Register | Register |
| Double Data I/O Option | Resync | Resync |
| Clock Pin Name | rgmii_rxc | rgmii_rxc |
| Pin Name (HI) | rgmii_rxd_HI | rgmii_rx_ctl_HI |
| Pin Name (LO) | rgmii_rxd_LO | rgmii_rx_ctl_LO |
Note: Due to the limited availability of GPIO pins with capability on
the Trion T120 BGA324 development board, the example design with
external PHY targeting this device cannot assign the RGMII control signals
(
rgmii_tx_ctl and rgmii_rx_ctl) to a standard DDIO
block.To accommodate for this specific hardware limitation, the following
workaround is implemented in
tsemac_ex.v:assign rgmii_tx_ctl = rgmii_tx_ctl_HI | rgmii_tx_ctl_LO;
assign rgmii_rx_ctl_HI = rgmii_rx_ctl;
assign rgmii_rx_ctl_LO = rgmii_rx_ctl;| Parameter | Setting | |
|---|---|---|
| rgmii_rxd [3:0] | rgmii_rx_ctl | |
| Mode | Input | Input |
| Register Option | Register | Register |
| Double Data I/O Option | Pipeline | Pipeline |
| Clock Pin Name | rgmii_rxc | rgmii_rxc |
| Pin Name (HI) | rgmii_rxd_LO | rgmii_rx_ctl_LO |
| Pin Name (LO) | rgmii_rxd_HI | rgmii_rx_ctl_HI |
In the Efinity Interface Designer, use the Create Block/ Create Bus menu to add these signals and configure them according to Table 1 and Table 2.
Figure 1 and Figure 2 illustrate the conversion from RGMII RX to RX AXI ST at 1000 Mbps with the recommended block editor settings in Table 1 and Table 2.