Generating the Example Design

Use the following steps to generate the example design from the IP Catalog.
  1. Create a new project.
  2. Select the Triple Speed Ethernet MAC core from the IP Catalog and set the following configurations.
    • Turn on Use MAC with Transceiver option.
    • Maximum Transmission Unit Frame Length:: 16018
  3. In the Deliverables tab, turn on the Example Design (Ti375N1156_devkit).
  4. Click Generate.

The example design is available in <project path>\ip\<ip-module-name>\Ti375N1156_devkit directory.

To run the example design in Auto Negotiation mode (default):
  1. Open the example design at <project path>\ip\<ip-module-name>\ efx_ethernet_1g_exp.xml
  2. Compile the design.
  3. Download the design to the Titanium Ti375 N1156 Development Kit.
  4. Based on the macros enabled, read the auto negotiation advertised abilities register for the lane in PHY mode.
  5. Then, override the following bits:
    • Bit 12 = 1'b1 (Full duplex)
    • Bit [11:10] = 2'b01 (100 Mbps)
    • Bit 15 = 1 (Link up)
  6. Upon assertion of PHY_INIT_DONE, write the corresponding signal_ok register bit to 1 to enable the RX path.
  7. The test passes when:
    • ln_data_cnt and ln_frame_cnt increments.
    • ln_err_cnt and ln_bad_frame_cnt remained 0.
To run the example design in 2.5G Jumbo mode:
  1. Open the example design at <project path>\ip\<ip-module-name>\ efx_ethernet_1g_exp.xml
  2. Change the Speed option to 2.5Gbps for both Lane 0 and Lane 3 in the Interface Designer.
  3. Press the Generate Interface Output files.
  4. Only enable the JUMBO macro in Project Editor.
  5. Compile the design.
  6. Download the design to the Titanium Ti375 N1156 Development Kit.
  7. Upon assertion of PHY_INIT_DONE, write the corresponding signal_ok register bit to 1 to enable the RX path.
  8. The test passes when:
    • ln_data_cnt and ln_frame_cnt increments.
    • ln_err_cnt and ln_bad_frame_cnt remained 0.

Table 1. Transceiver Example Design Project Files
File Name Description
efx_ethernet_1g_exp.sv Example design of top-level wrapper.
<user_given_ip_name>.sv 1 The generated Triple Speed Ethernet MAC core file is based on the user configuration in Efinity IP Manager.
Timing_Ti375.sdc Constraint file for example design.
efx_mac1gbe_exp_apb_master.sv1 APB master controller module.
efx_mac1gbe_exp_apb_decoder.v 1 APB address decoder module.
efx_mac1gbe_exp_pat_gen.sv Pattern generator module.
efx_mac1gbe_exp_checker.sv Checker module to validate data received.
Efx_mac1gbe_exp_speed_ctrl.sv 1 Auto negotiation sequence module.
debug_top.v Verilog file for EFX debug module.
debug_profile.json Virtual I/O Debugger core file. Load this file in the Efinity Virtual I/O Debugger to customize the example design. See Virtual I/O Debugger Settings.
1 This module is encrypted.