RGMII Dynamic Clock Switch (Titanium only)
In RGMII interfaces, clock-to-data skew caused by PCB trace length mismatches between the
clock (rgmii_rxc) and data (rgmii_rxd) lines is a
critical factor that affects reliable data sampling. At 1000 Mbps, even a small
difference in trace length can lead to a timing misalignment of several hundred ps which
is significant for double data rate (DDR) sampling.
To compensate for this skew and ensure that the clock edge is properly aligned with the center of the data valid window, the example design uses a PLL with core feedback. The PLL reconstructs an internal receive clock that is phase-aligned with the incoming RGMII signals at the FPGA input pins, effectively cancelling the skew introduced by PCB routing. This ensures accurate setup and hold timing at 1000 Mbps operation.
rgmii_rxc) provided by the external PHY operates at
different frequencies depending on the negotiated Ethernet link speed:- 2.5 MHz for 10 Mbps
- 25 MHz for 100 Mbps
- 125 MHz for 1000 Mbps
Because the PLL input path has a minimum input frequency requirement and cannot reliably lock at very low frequencies such as 2.5 MHz, a dynamic clock mux is implemented to support all link speeds.
- At 10/100 Mbps, the RX clock is too slow for PLL operation, so the PHY RX clock is routed directly through the GPIO input path.
- At 1000 Mbps, the faster 125 MHz RX clock is routed through the PLL, enabling phase alignment with core feedback to compensate for PCB trace mismatch and maintain timing accuracy.
This allows the same RGMII interface to dynamically support 10/100/1000 Mbps operation while maintaining clock integrity, data alignment and timing reliability across all link speeds, even when PCB trace skew between the clock and data lines exists.
