Customizing the Triple Speed Ethernet MAC

The core has parameters so you can customize its function. You set the parameters in the General tab of the core's IP Configuration window.

Table 1. Triple Speed Ethernet MAC Core Parameters
Name Options Description
TSE MAC Version Any Triple Speed Ethernet MAC version.
Default: 16
Use MAC with Transceiver Enable, Disable Enables use of the Triple Speed Ethernet MAC Core with FPGA transceiver (available only on supported devices). When checked, the following options are auto-configured:
  • PHY Interface Type: SGMII
  • AXI4 Data Width: 16
  • TX FIFO: Disable
  • RX FIFO: Disable
  • Register Interface: APB
Default: Disable
PHY Interface Type RGMII, MII, RMII, GMII, SGMII Defines the PHY interface type.
Default: RGMII
AXI4 Data Width 8, 16, 32 Defines AXI4-Stream data width.
Default: 8
TX FIFO Enable, Disable Enables or disables the TX FIFO in the core. Must be enabled if tx_axis_clk ≠ PHY clock frequency. See Store Forward Mode.
Default: Enable
TX FIFO Depth 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384 Defines TX FIFO depth.
Must be greater than frame length. For jumbo frames > 16384, TX FIFO must be disabled. See Store Forward Mode for minimum depth requirements.
Default: 2048
RX FIFO Enable, Disable Enables or disables the RX FIFO. Must be enabled if rx_axis_clk ≠ PHY clock frequency.
Default: Enable
RX FIFO Depth 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384 Defines RX FIFO depth.
Default: 2048
Programmable Inter Packet Gap 8 – 63 Default value for tx_ipg_length.
Default: 12
Note: In Store-Forward mode, the effective IPG may be governed by the buffering mechanism.
Maximum Transmission Unit Frame Length 64 – 16018 Default value for frm_length. Includes headers, payload, and FCS.
Received frames larger than maximum tranmission unit (MTU) are flagged as oversized; payloads < 46 bytes (or < 42 bytes for VLAN Tagged frames) are flagged as undersized.
Default: 1518
MAC Source Address Any Default value for mac_addr. Used when generating TX pause frames and for address filtering comparison.
Default: 48'h0000_0000_0000
Broadcast Filtering Enable, Disable Default value for broadcast_filter_en.
Default: Enable
Enable local loopback support Enable, Disable Enables or disables local loopback capability on the selected PHY interface. When checked, loop_ena can be toggled at run time to enable or disable loopback.
Default: Disable
RGMII Transmit Clock Delay Enable (Center-aligned), Disable (Edge-aligned) Defines alignment of RGMII transmit clock (rgmii_txc) with data (rgmii_txd). Applies to 10 / 100Mbps only.
Default: Enabled (Center-aligned)
First sampling of RGMII Receive Data Falling Edge, Rising Edge Defines the first sampling edge for RGMII receive data. Applies to 1000 Mbps only.
Default: Falling edge
Register Interface AXI4-Lite, APB Defines register interface for accessing the control and status registers in Control and Status Registers.
Default: AXI4-Lite

The maximum capabilities of the Triple Speed Ethernet MAC core depend on the FPGA device family and speed grade.

Table 2. Triple Speed Ethernet MAC core Maximum Capabilities
Device Family Lower speed grade Higher speed grade
Trion
Max speed: 1 Gbps
Jumbo packet size: Up to 4 kB for Store-Forward Mode
Topaz
(Except for SGMII with AXI Data Width = 8)
Titanium
Note:
  • Lower speed grade refers to C3 for Trion and Titanium devices, and C2 for Topaz devices.
  • Higher speed grade refers to C4 for Trion and Titanium devices, and C3 for Topaz devices.