Virtual I/O Debugger Settings
This example design has a Virtual I/O Debugger interface to probe and control the signals of the example design. To control the settings, refer to the Virtual I/O Debugger settings.
Note: In the following table, the signal names are prefixed with
l0_ and l3_, to indicate and distingush these
instances. For a detailed signal description, refer to Titanium SGMII 1G and 2.5G User Guide and Table 1.| Signal Name | Width | Probe / Source | Description |
|---|---|---|---|
| General Signals | |||
| pll_locked | 1 | Probe | Lock signal from PLL, indicating that the clock sources
(INIT_CLK and APB_CLK) are stable.
This signal kicks start the operation of the example design,
where the assertion of PLL_LOCK releases the resets
in the Triple Speed Ethernet MAC core and the FPGA PCS. |
| PCS Interface | |||
| Instance Lane 0 | Refer to the signal descriptions in Signals per
Quad table in the Signals chapter of Titanium SGMII 1G and 2.5G User Guide. |
||
| l0_sync_status | 1 | Probe | |
| l0_sgmii_speed | 2 | Probe | |
| Instance Lane 3 | |||
| l3_sync_status | 1 | Probe | |
| l3_sgmii_speed | 2 | Probe | |
| Triple Speed Ethernet MAC Interface | |||
| pma_cmn_ready | 1 | Probe | Refer to the signal descriptions in Table 1. |
| Instance Lane 0 | |||
| l0_init_done | 1 | Probe | |
| l0_rx_signal_detect | 1 | Probe | |
| Instance Lane 3 | |||
| l3_init_done | 1 | Probe | |
| l3_rx_signal_detect | 1 | Probe | |
| APB Interface and Status | |||
| usr_apb_start | 1 | Source | This signal enables you to manually trigger APB
requests. Efinix recommends that you
control this signal by selecting Active-High
from the drop-down list in the control column. This signal
operates based on its rising edge, i.e., the assertion of this signal
triggers 1 APB request. Prior assertion of this signal, APB signals
(usr_apb_write, usr_apb_addr, and
usr_apb_pwdata) need to be assigned and
stable.To trigger another APB request, this signal needs to
return to 0 first, then reassert to trigger the
subsequent APB request. |
| usr_apb_write | 1 | Source | APB Write. |
| usr_apb_addr | 24 | Source | APB Address. |
| usr_apb_pwdata | 32 | Source | APB Write Data. |
| Auto Negotiation Interface | |||
| Instance Lane 0 | The assertion of this signal indicates that the auto negotiation sequence is ongoing and no APB access is allowed. | ||
| l0_speed_chg_active | 1 | Probe | |
| l3_speed_chg_active | 1 | Probe | |
| Checker | |||
| l0_data_cnt | 8 | Probe | Data counter—Increments on every cycle when valid data is received on the MAC RX AXI ST Interface |
| l3_data_cnt | 8 | Probe | |
| l0_err_cnt | 8 | Probe | Error counter—Increments on every cycle when erroneous data is received on the MAC RX AXI ST Interface |
| l3_err_cnt | 8 | Probe | |
| l0_frame_cnt | 8 | Probe | Frame counter—Increments for every frame received on the MAC RX AXI ST Interface |
| l3_frame_cnt | 8 | Probe | |
| l0_bad_frame_cnt | 8 | Probe | Bad frame counter—Increments for every bad frame received on the MAC RX AXI ST Interface |
| l3_bad_frame_cnt | 8 | Probe | |