Block Diagram

The Triple Speed Ethernet MAC core or efx_mac1gbe comprises of the following modules:

Power-up sequence to handshake with the FPGA transceiver in SGMII mode.
AXI4-stream user interface
TX engine with CRC generation
RX engine with CRC checker
PHY interface
Statistics reporting
Priority flow control module
Broadcast and address filtering

Figure 1 shows the modules inside the Triple Speed Ethernet MAC core.

Figure 1. Triple Speed Ethernet MAC Core Sub-Modules

Note: The power-up sequence module is instantiated for SGMII mode only. Details of the power-up sequence are described in Power Up Handshake with FPGA Transceiver.