Clock Sources

The core has 2 independent clock sources:
  • init_clk
  • mac10gbe_clk
Table 1. Core Clock Sources
Clock Name Frequency Description
INIT_CLK ≤ 50 MHz To facilitate the power-up sequence of the transceiver PHY.
Can be sourced from the PLL or CLKIN pin.
MAC10GBE_CLK 156.25 MHz Sourced from the transceiver forwarded clock to be the source synchronous.
Eliminates additional clock PPM.
The forwarded clock is used to clock the 10G PCS in the transceiver.

The Figure 1 shows the clock domains in the core.

Figure 1. Core Clock Domain