Using the PHY RGMII Clock-to-Data Delay (Trion only)

For Trion devices, you can control the transmit and receive clock delay of the PHY through the Sapphire SoC software driver.

This is done using the PhyDlySetRXTX() function in the main.c file.

To adjust the TX_delay and RX_delay, modify the function call in: \embedded_sw\sapphire\software\standalone\tseDemo\src\main.c

This method allows flexible software-level tuning of the PHY delay values to achieve optimal RGMII clock-to-data alignment for both transmit and receive paths.

void main() {
    u32 prompt=0;
    u32 speed;

    PhyNego(1);	
    bsp_init();
    if(TEST_MODE == 1){
    	bsp_print("===   TSEMAC Example Design in Linked-Partner Mode   ===");
    } else {
    	bsp_print("===   TSEMAC Example Design in Normal Mode   ===");
    }
    PhyDlySetRXTX(8, 0); //change PHY RX_Delay and Tx_Delay settings here
    speed = PhyNormalInit();
    MacNormalInit(speed);
    StartRunning();
}