Realigning the PHY Clock

To ensure proper transmission and reception, the PHY clock must be correctly aligned with the data signals:

There are two ways to realign the PHY clock with respect to data:
  • Option 1: Use the PHY RGMII clock-to-data delay in the Sapphire SoC software driver function.
  • Option 2: Configure the RGMII Transmit Clock Delay and First Sampling of RGMII Received Data parameter in the General tab of the IP Configuration window.