XGMII TX

At XGMII TX, the core outputs the TX Ethernet frames based on the following priority in descending order:
  1. Faulty link condition
  2. Pause mechanism from the RX pause frame
  3. Request to send TX pause frame
  4. TX_AXI_TVALID, TX_AXI_TLAST, TX_AXI_TKEEP, TX_AXI_TDATA, and TX_AXI_TUSER.
Data transfer from the TX_AXI interface takes the lowest priority. The core converts TX_AXI_TDATA directly into XGMII_TXD. Hence, TX_AXI_TDATA must start with header information, i.e., destination address, source destination, Ethernet length or type, and/or VLAN tags.
Note: In all figures containing TX_AXI_TDATA, the header octets are labeled DATA to illustrate the conversion between the TX AXI interface and the XGMII TX.

Figure 1. Conversion from TX AXI ST to XGMII TX

Priority flow control takes 2nd and 3rd priority, while a faulty link condition has the highest priority. Whenever a higher-priority event arrives at the TX channel, it needs to wait for the ongoing transfer to complete before the higher-priority event takes effect. Details of priority handling are described in Priority Flow Control (Duplex Mode) and Link Fault Sequence.

Based on the user defined Programmable Inter Packet Gap, XGMII TX also inserts the minimum inter packet gap (IPG) between data frames and/or TX pause frames. However, faulty link condition and RX pause mechanism start at Octet 0 without the minimum IPG.

Refer to Figure 1, Figure 2, Figure 1, Figure 1, and Figure 2 for more details on the priority handling and IPG insertion at XGMII TX.