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Introduction
Features
Device Support
Resource Utilization
Release Notes
Functional Description
Block Diagram
Clock Sources
Reset Signals
Power Up Handshake with FPGA Transceiver
Ethernet Packets, Frames, and IPG
User Interface AXI4-Stream
TX AXI ST Interface
RX AXI ST Interface
CRC Generation and Check
Programmable Inter Packet Gap (IPG)
TX PHY Interface
RGMII TX
MII TX
RMII TX
GMII TX
SGMII TX
RX PHY Interface
RGMII RX
MII RX
RMII RX
GMII RX
SGMII RX
Data Streaming Modes for Transmission
Cut Through Mode
Cut Through Mode with Width Adaptation
Store Forward Mode
Data Streaming Modes for Reception
Cut Through Mode
FIFO Mode
Automatic Padding for Short TX Frames
Terminating Bad TX Frames
Non-Compliant tx_axis_mac_tlast
Assertion of tx_axis_mac_tuser
Non-Streaming TX Data
Dropped tx_axis_mac_tvalid Before End of Frame
TX FIFO Overflow
Erroneous RX Frame
Undersized RX Frame
Oversized RX Frame
Frame Check Sequence (FCS) Error
Mismatched Length RX Frame
Non-Streaming RX Data Frame (SGMII)
Error Frame
Address Filtering and Broadcast Filtering at RX
Priority Flow Control (Duplex Mode)
Send Pause Frame at TX
Decoding Pause Frame at RX
Statistic Reporting
aFramesTransmittedOK
aTxPAUSEMACCtrlFrames
ifOutErrors
aTxFifoOverflowFramesErrors
aTxIncontinuityFramesErrors
aFramesReceivedLen
etherStatsUndersizePkts
etherStatsOversizePkts
aRxFrameMismatchedLength
aFrameCheckSequenceErrors
aRxFilterFramesErrors
aRxPAUSEMACCtrlFrames
ifInErrors
aFramesReceivedOK
etherStatsPkts
Latency
IP Manager
Customizing the Triple Speed Ethernet MAC
Hidden Options
NO_PREAMBLE
Ports
Control and Status Registers
Triple Speed Ethernet MAC Example Design
Example Design with External PHY
Required Hardware
Hardware Set Up for Trion® T120 BGA324 Development Board
Set Up a USB-to-UART Module
Hardware Set Up for Titanium Ti60 F225 Development Board
Set Up a USB-to-UART Module
Using the Example with the RISC-V SDK
Test Modes
Normal Mode Test
Linked Partner Test
Realigning the PHY Clock
Using the PHY RGMII Clock-to-Data Delay (Trion only)
RGMII Dynamic Clock Switch (Titanium only)
Using Wireshark
Example Design Configuration Registers
Example Design with FPGA Transceiver
Available Macros in the Transceiver Example Design
Enabling the Macros in the Transceiver Example Design
Generating the Example Design
Virtual I/O Debugger Settings
Triple Speed Ethernet MAC Testbench
Differences with Ethernet 10G MAC Core
Revision History
Priority Flow Control (Duplex Mode)
The
core supports the flow control at TX and RX duplex mode.