TX AXI ST 64

At the TX AXI ST interface, transmission starts when TX_AXI_TREADY = 1. The assertion of TX_AXI_TREADY indicates that the core is ready to accept the TX data streaming.

To transmit, assert TX_AXI_TVALID, along with TX_AXI_TDATA, TX_AXI_TKEEP, TX_AXI_TLAST, TX_AXI_TUSER. TX_AXI_TDATA contains 64-bit data streaming to be transmitted to XGMII_TXD. TX_AXI_TLAST indicates the last byte of data in the data stream. TX_AXI_TKEEP indicates the positional validity of the byte data within the data streaming. The assertion of TX_AXI_TUSER indicates an error in the data streaming.

For Ethernet applications, TX_AXI_TDATA must contain streaming data, i.e., data needs to be streaming and continuous, where TX_AXI_TKEEP = FF except at TX_AXI_TLAST. Streaming data, at TX_AXI_TLAST, means TX_AXI_TKEEP = {01, 03, 07, 0F, 1F, 3F, 7F, FF}. Refer to Figure 1.

If the data is not continuous, it is interpreted as a bad frame and is dropped. The same goes with TX_AXI_TUSER, i.e., the asserted TX_AXI_TUSER results in a bad frame. Refer to Terminating Bad TX Frames.

When TX_AXI_TREADY = 0, the core is not ready to accept any TX data. Hence, you need to hold or retain all the current TX_AXI signals, which are TX_AXI_TDATA, TX_AXI_TLAST, TX_AXI_TVALID, TX_AXI_TKEEP, and TX_AXI_TUSER, until TX_AXI_TREADY recovers to 1. Refer to Figure 2.

Figure 1. Streaming Data at TX AXI ST Interface

Figure 2. User to Retain TX_AXI Signals Until TX_AXI_TREADY Recovers

When TX_AXI_TREADY = 1, the core effectively decodes when TX_AXI_TVALID is asserted. When TX_AXI_TVALID = 0, the entire column of TX_AXI signals (TDATA, TKEEP, TLAST, TUSER) is deemed as invalid. Refer to Figure 3.

Figure 3. Invalid TX_AXI Signals Column When `TX_AXI_TVALID` = `0`

Important: The user interface AXI ST 64 operates in mac10gbe_clk domain. You need to ensure that the TX_AXI_TVALID, TX_AXI_TDATA, TX_AXI_TKEEP, TX_AXI_TLAST, and TX_AXI_TUSER signals are registered and synchronous to mac10gbe_clk prior to entering the core.