i2cMasterInterruptDemo Design

This example is based on the i2cMasterDemo for the Sapphire SoC, with an important enhancement on the timeout interrupt handling. It demonstrates how the Sapphire SoC operates as an I²C master and utilizes a timeout interrupt mechanism to detect and recover when an I²C slave is not responding.

When a timeout occurs (i.e., no slave response within the expected time), the CPU exits the transmission loop and triggers an external interrupt. This prevents the CPU from getting stuck indefinitely during I²C communication errors.

Once the I²C master is able to connect to the I²C slave, the program triggers the transmission and reception of data, initially with a single byte, and subsequently with a larger chunk of 20 bytes data. By default, the conﬁguration assumes the slave device is set to transmit a 1-byte register address. For 2-byte register addresses, you need to modify the deﬁnition of WORD_REG_ADDR to 1.

The design displays these messages in a UART terminal:

i2c Master Demo!
Please ensure you 've either connect to a compatible I2C Slave or running the i2CSlaveDemo 
with I2C ports connected.   
TEST STARTED!

Note: The I²C transfer is dropped when a timeout occurs, indicating the I²C slave is not found within the allowed response window:

i2c Master Demo!
Please ensure you 've either connect to a compatible I2C Slave or running the i2CSlaveDemo 
with I2C ports connected.   
TEST STARTED!
I2C Transfer is dropped due to timeout!