Functional Description

The watchdog timer in Sapphire SoC has a prescaler and two counters, offers a 2-stage interrupt/panic.

Figure 1. Sapphire SoC Watchdog Timer Clock Diagram

The watchdog timer has two counters, counter 0 and counter 1. Both counters run simultaneously and each counter has its own limit. When the software resets the watchdog timer, both counters reset too. If the watchdog timer does not reset,

  • When counter 0 has reached its limit:
    1. The watchdog timer sends an interrupt to the PLIC, which is triggered as an external interrupt in the software.
    2. During the interrupt routine, you can try to recover the software or prepare for a proper shutdown or reset.
  • When counter 1 has reached its limit:
    1. The watchdog timer asserts the top level pin, system_watchdog_hardPanic.
    2. You can use the signal from this pin to implement their reset or recovery logic for the system.