Migrating to the Sapphire SoC v2.0 from a Previous Version
The Sapphire SoC v2.0 available in the Efinity software v2021.2 has many new features compared to previous versions, and the IP Configuration wizard and drivers are updated to reflect these new features. Therefore, you cannot automatically migrate an existing design to v2.0. If you want to migrate to v2.0, the following sections provide some guidelines.
IP Configuration Wizard
The configuration options for the Sapphire SoC v2.0 support new features such as more configurable caching, FPU, MMU, and a peripheral clock. Use the following settings to create a v2.0 SoC that is similar to previous versions.
| Tab | Option | Setting | Notes |
|---|---|---|---|
| SOC | Peripheral Clock | DISABLE | In v1.x, the APB3 peripherals are driven by the system clock. In v2.0, set this option to DISABLE. |
| Custom Instruction | DISABLE | Not supported in v1.x | |
| Linux Memory Management Unit | DISABLE | ||
| Floating-point Unit | DISABLE | ||
| Atomic extension | DISABLE | ||
| Cache/Memory | Data Cache Way | 1 | In v1.0, the SoC has a fixed I$ and D$ cache way (1
way) and size (4 KB). In v1.1, the wizard supports 1 ways and 1
KB, 2 KB, 4 KB, 8 KB, 16 KB, or 32 KB |
| Data Cache Size | 4 KB (v1.0) 1 KB, 2 KB, 4 KB, 8 KB, 16 KB, or 32 KB
(v1.1) |
||
| Instruction Cache Way | 1 | ||
| Instruction Cache Size | 4 KB (v1.0) 1 KB, 2 KB, 4 KB, 8 KB, 16 KB, or 32 KB
(v1.1) |
||
| External Memory AXI3 Interface | DISABLE (v1.0) ENABLE or DISABLE (v1.1) |
In v1.x, an external memory interface is not supported with a cacheless CPU | |
| On-Chip RAM Size | 1 KB, 2 KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, 256 KB, or 512 KB | The v1.x SoC supports fewer sizes for On-Chip RAM. Choose one of these options in v2.0 for compatibility. | |
| Debug | Target OpenOCD | See v2.0 options | This option is not supported in v1.0. This option is the same
in v1.1 and v2.0. |
| Custom Target OpenOCD | See v2.0 options | This option is not supported in v1.0. This option is the same
in v1.1 and v2.0. |
|
| OpenOCD Debug Mode | Any | This option is not supported in v1.x. However, you can choose either option because it sets IDE environment variables and does not affect the SoC. |
Debug Configuration
The default_softTap debug configuration file is updated in v2.0. Therefore, you cannot use the default_softTap generated with v1.1 with v2.0. If you are using v2.0, you need to remove the old default_softTap debug configuration from your Eclipse project and import the v2.0 one. See Appendix: Import the Debug Configuration for instructions. Importing the Debug Configuration is not applicable if you are using Efinity RISC-V Embedded Software IDE as the IDE generates the debug configuration during the import project wizard.
Application Software
In v2.0, there are several changes to the generated embedded software:
- SoC device names and definitions—The device names and definitions in the soc.h file are updated. The v2.0 embedded software includes the file compability.h, which converts the naming from v1.x to v2.0. Include compability.h at the top of your software application code to convert the names. You can also reference the example compabilityDemo in the /embedded_sw/<module name>/software/standalone folder.
- Core timer driver—The machine timer is replaced with the Clint timer, which is a native CPU timer. The software driver code is slightly different than the code for the machine timer. To convert from the machine timer function to the Clint timer function, include the compability.h and bsp.h at the top of your software application code.