Customizing the Sapphire SoC

There are two options available for the Sapphire SoC, which provides for different needs and applications:

Standard—Best performance. This option utilizes more area of resources to achieve the best performance. Advanced features are only available in this option.
Lite—Smallest area. This option utilizes a small area of resources by limiting the Sapphire SoC performance. Advanced features are not available in this option.

You customize the Sapphire SoC using the IP Configuration wizard. The parameters are arranged on tabs so you can click through them more easily.

There will be differences in the SOC and Cache/Memory tabs depending on the chosen option, either Standard or Lite, but all the other tabs are the same across both options.

Table 1. Sapphire SoC Tab Parameters
Parameter	Options	Description	Availability
Option	Standard, Lite	This option in the Sapphire SoC provides for different applications. Default: Standard	Standard and Lite
Core Number	1 - 4	Enter the number of CPU cores. Default: 1	Standard only
Frequency (MHz)	20 - 400	Enter the frequency in MHz. Default: 100	Standard and Lite
Peripheral Clock	On, off	Choose whether you want to run a dedicated clock for the APB3 slaves (SPI, I2C, GPIO, UART, and user timer) and AXI4 master.	Standard and Lite
Peripheral Clock Frequency (MHz)	20 - 200	Enter the peripheral clock frequency in MHz.	Standard and Lite
Cache	On, off	Choose whether you want to include I$ and D$ caches.	Standard and Lite
Data Cache	On, off	Choose whether to include D$ cache. This parameter is only available when `Cache` parameter is turned on. You may choose to include I$ cache only or include both I$ and $D caches.	Lite only
Custom Instruction	On, off	Choose whether to enable the custom instruction interface.	Standard only
Linux Memory Management Unit	On, off	Choose whether to enable the Linux MMU.	Standard only
Floating-point Unit	On, off	Choose whether to enable the FPU.	Standard only
Floating-point Extension	F-Extension Only, F and D-Extension	Choose whether to enable single or double precision for FPU.	Standard only
Atomic Extension	On, off	Choose whether to enable atomic extension instruction support. If you enable the Linux MMU, this option must be enabled and is turned on by default.	Standard only
Compressed Extension	On, off	Choose whether to enable compressed instruction support.	Standard only
Multiplication and Division	On, off	Choose whether to enable multiplication and division, which is the RISC-V M extension. Note: This feature is turned on in Standard option.	Lite only
Barrel Shifter	On, off	Choose whether to include the barrel shifter, which is a module that can perform shift operations on any number of bits within a single clock cycle. Note: This feature is turned on in Standard option.	Lite only
CSR Optimization	On, off	Choose whether to minimize the number of RISC-V Control and Status Registers. Note: This feature is turned off when the RISC-V standard debug interface is enabled. This feature is also turned off in Standard option.	Lite only

Important: When running the SoC at high frequencies, Efinix recommends that you use the TIMING_1 place and route optimization. To set this option:

1. Open the Project Editor.

2. Click the Place and Route tab.

3. Double-click the Value cell for --optimization_level.

4. Choose TIMING_1.

5. Click OK and then compile.

Table 2. Sapphire Cache/Memory Tab Parameters
Parameter	Options	Description	Availability
Data Cache Way	1, 2, 4, 8	Choose the number of ways for the data cache. Default: 1	Standard and Lite
Cache Size	1 KB, 2 KB, 4 KB, 8 KB, 16 KB, 32 KB	Choose the size of the data cache. Default: 4 KB	Standard and Lite
Instruction Cache Way	1, 2, 4, 8	Choose the number of ways for the instruction cache. Default: 1	Standard and Lite
Cache Size	1 KB, 2 KB, 4 KB, 8 KB, 16 KB, 32 KB	Choose the size of the instruction cache. Default: 4 KB	Standard and Lite
External Memory Interface	On, off	On: By default. Instantiate the external memory interface. Off: Do not use the external memory interface.	Standard and Lite
AXI Interface Type	On, off	On: Use an AXI4 full duplex interface. Off: By default. Use an AXI3 half duplex interface.	Standard and Lite
AXI Interface Optimization	Optimize for area, Optimize for bandwidth	Optimize for area: Smaller area but lower bandwidth. Optimize for bandwidth: Full bandwidth but uses more resources.	Lite only
External Memory Clock Domain	Unified System Clock, Dedicated Memory Clock	Unified System Clock: The external memory interface will use the system clock (io_systemClk). This will utilize lesser resource as no CDC logic is required. Note: By sharing the system clock, the frequency of the system clock will be limited by the slowest domain in the system. Dedicated Memory Clock: The external memory interface will use the dedicated memory clock (io_memoryClk). This will utilize more resource.	Lite only
External Memory Data Width	32, 64, 128, 256, 512	Choose the data width for the AXI interface. Default: 128	Standard and Lite
External Memory AXI ID Width	6, 8	Choose the width of AXI ID.	Standard and Lite
External Memory AXI3 Address Size	4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB, 256 MB, 0.5 GB, 1 GB, 1.5 GB, 2 GB, 2.5 GB, 3 GB, 3.5 GB	Choose the address size for the AXI interface. Default: 3.5 GB	Standard and Lite
On-Chip RAM Size	1 KB, 2 KB, 4 KB, 8 KB, 16 KB, 24 KB, 32 KB, 48 KB, 64 KB, 80 KB, 96 KB, 128 KB, 144 KB, 160 KB, 192 KB, 224 KB, 256 KB, 384 KB, 512 KB	Choose the size of the internal BRAM. Default: 4 KB	Standard and Lite
Custom On-Chip RAM Application	On, off	On: Overwrite the default SPI flash bootloader with the user application. Off: By default. Use the default SPI flash bootloader.	Standard and Lite
User Application Path	–	Enter the path to your target user application. The file must be in .hex format.	Standard and Lite

Table 3. Sapphire Debug Tab Parameters
Parameter	Options	Description
Connection Type	Standalone, Chain	Choose whether you want to include the chain debug feature to the SoC. This allows the connection of multiple devices for JTAG debugging with a daisy-chain. Else, select as standalone. Standalone: By default. The debug feature is available for the standalone SoC only. Daisy-chain: The debug feature extends to multiple devices or SoC in the chain. Once enabled, you can debug multiple devices with a single debugger.
RISC-V Standard Debug	On, off	Choose whether to enable the RISC-V standard debug interface. On: Use the debug module that follows the RISC-V External Debug Support Version 0.13. (Recommended)¹ ² Off: Use debug module that is customized for the VexRiscv core.
Hardware Breakpoint	0 - 4	Number of hardware breakpoints. This hardware breakpoint is a program type breakpoint. Only applicable when the RISC-V Standard debug is turned on.
Additional Tap Devices (Max)	1 - 8	The maximum number of extra devices in the chain. This option is only applicable when you are using daisy-chain connection type. Default: 1
Soft Debug Tap	On, off	Choose whether you want to include a soft debug TAP for debugging. Off: By default. The SoC uses the JTAG User TAP interface block to communicate with the OpenOCD debugger. On: The SoC has a soft JTAG interface to communicate with the OpenOCD debugger. You need to use this setting if you want to use the soft JTAG interface instead of the JTAG User TAP.
FPGA Tap Port	1, 2, 3, 4	Choose which Tap port you want to target with the OpenOCD debugger. This option is only applicable when you are using the JTAG User Tap interface block to communicate with the OpenOCD debugger.
Target Board/Cable/Module	Trion T120 BGA324 Development Board Trion T120 BGA576 Development Board Trion T20 BGA256 Development Board Xyloni Titanium Ti60 F225 Development Board Titanium Ti180 J484 Development Board C232HM-DDHSL-0 (Soft debug) FTDI Module FT2232H (Soft debug) FTDI Module FT4232 (Soft debug) ISX-DLC_EF001 Programming Cable Custom	Choose which board you want to target with OpenOCD. Choose Custom to target your own board.
IDE Selection	Legacy Eclipse IDE (OpenOCD v0.10) Efinity RISC-V IDE (OpenOCD v0.11)	Choose which debug script format you want to generate. This selection allows you to roll back to target the Legacy Eclipse IDE. By default, Efinity RISC-V Embedded Software IDE is targeted.
Custom Target Board	–	Enter the name of your board.
Application Region Size	124KB, 252KB, 508KB, 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB, 128MB, 256MB	Modify the linker script to outline the region for the user application. This option is only applicable for SoCs with external memory. For SoCs with internal memory, the region size is determined by the on-chip RAM size.
Application Stack Size	1KB, 2KB, 4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB, 128MB	Modify the linker script to specify the application stack size. This option is only applicable for SoCs with external memory. For SoCs with internal memory, the region size is automatically set to 1/8 of the on-chip RAM size.
OpenOCD Debug Mode	Turn on by default Turn off by default	Choose whether you want software applications to run in debug mode by default or not. See Debug with the OpenOCD Debugger for more details.

Table 4. Sapphire UART Tab ParametersWhere n is 0, 1, or 2
Parameter	Options	Description
UART n	On, off	On: Instantiate the interface. Off: Do not use the interface.
UART n Interrupt ID	1 - 36	Choose the interrupt ID for the UART. The IDs default to: UART 0: 1 UART 1: 2 UART 2: 3
UART n FIFO Depth	64, 128, 256	Specify the depth of UART’s FIFO.

Table 5. Sapphire SPI Tab ParametersWhere n is 0, 1, or 2.
Parameter	Options	Description
SPI n	On, off	On: Instantiate the interface. Off: Do not use the interface.
SPI n Interrupt ID	1 - 36	Choose the interrupt ID for the SPI. The IDs default to: SPI 0: 4 SPI 1: 5 SPI 2: 6
SPI n Data Width	8 - 16	Configure the data width for the SPI interface. Note: Only applicable for SPI 1 and SPI 2.
SPI n Chip Select Width	1 - 8	Choose the number of Chip select required for the SPI interface. Note:
SPI n FIFO Depth	64, 128, 256, 512, 1024, 2048	Specify the depth of SPI’s FIFO.

Table 6. Sapphire I2C Tab ParametersWhere n is 0, 1, or 2.
Parameter	Options	Description
I2C n	On, off	On: Instantiate the interface. Off: Do not use the interface.
I2C n Interrupt ID	1 - 36	Choose the interrupt ID for the I²C. The IDs default to: I2C 0: 8 I2C 1: 9 I2C 2: 10

Table 7. Sapphire GPIO Tab ParametersWhere n is 0 or 1.
Parameter	Options	Description
GPIO n	On, off	On: Instantiate the interface. Off: Do not use the interface.
GPIO n Bit Width	1, 2, 4, 8, 16, 32	Choose the number of pins for the GPIO. Default: 4 (GPIO 0), 8 (GPIO 1)
GPIO n Interrupt ID 0	1 - 36	Choose the interrupt ID for the GPIO. The IDs default to: GPIO 0: 12 GPIO 1: 14
GPIO n Interrupt ID 1	1 - 36	Choose the interrupt ID for the GPIO. The IDs default to: GPIO 0: 13 GPIO 1: 15

Table 8. Sapphire APB3 Tab ParametersWhere n is 0, 1, 2, 3, or 4.
Parameter	Options	Description
APB Slave Address Size	4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1MB	Choose the APB slave size. This setting applies to all APB slaves. Default: 64KB
APB3 Slave n	On, off	On: Instantiate the interface. Off: Do not use the interface.

Table 9. Sapphire AXI4 Tab ParametersWhere n is 0 or 1.
Parameter	Options	Description
AXI Master	On, off	On: Instantiate the interface. Off: Do not use the interface. Note: The Efinity software v2025.2 and higher uses AXI master instead of AXI slave as the interface name.
AXI Slave Size	1 KB, 2 KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, 256 KB, 512 KB, 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB, 256 MB	Choose the size of the AXI slave.
AXI Slave n	On, off	On: Instantiate the interface. Off: Do not use the interface. Note: The Efinity software v2025.2 and higher uses AXI slave instead of AXI master as the interface name.
AXI Master n Data Width	32, 64, 128, 256, 512	Choose the width of the AXI master. Do not specify an AXI master width that is larger than the external memory data width.

Table 10. Sapphire User Interrupt Tab ParametersWhere n is A, B, C, D, E, F, G, or H.
Parameter	Options	Description
User n Interrupt	On, off	On: Instantiate the interface. Off: Do not use the interface.
User n Interrupt ID	1 - 36	Choose the interrupt ID. The defaults are: User A Interrupt: 16 User B Interrupt: 17 User C Interrupt: 22 User D Interrupt: 23 User E Interrupt: 24 User F Interrupt: 25 User G Interrupt: 26 User H Interrupt: 27

Table 11. Sapphire User Timer Tab ParametersWhere n is 0, 1, or 2.
Parameter	Options	Description
User Timer n	On, off	On: Instantiate the interface. Off: Do not use the interface.
User Timer n Counter Width	12, 16, 32	Choose the counter bit width. Default: 12
User Timer n Prescaler Width	8, 16	Choose the prescaler bit width. Default: 8
User Timer n Interrupt ID	1 - 36	Choose the interrupt ID. The defaults are: User Timer 0: 19 User Timer 1: 20 User Timer 2: 21

Table 12. Sapphire Watchdog Timer Parameters
Parameter	Option	Description
Watchdog Timer	On, Off	On: Instantiate the interface. Off: Do not use the interface.
Watchdog Timer Prescaler Width	8, 16, 24, 32	Choose the prescaler bit width. Default: 24
Watchdog Timer Counter Width.	16, 24, 32	Choose the counter bit width. Default: 16
Watchdog Timer Interrupt ID	1 ~ 36	Choose the interrupt ID. Default: 32

Table 13. Sapphire Base Address Tab Parameters
Parameter	Options	Description
Address Assignment Method	AUTO, MANUAL	AUTO: Automatically assign an address to the enabled peripherals. MANUAL: The user can assign addresses to the enabled peripherals.
External Memory Base Address	–	Displays the base address. You cannot change it.
AXI Master Base Address	–	Displays the base address when the Address Assignment Method is set to AUTO. When the Address Assignment Method is Manual, enter the base address value. The wizard automatically rounds the value to 16 MB aligned addresses during IP generation. For example, 0x41234567 is rounded to 0x41000000. Note: When external memory is disabled and auto address assignment is used, the AXI master is assigned to 0x0100_0000 to preserve the Sapphire memory space. However, you can set the desired base address in manual address assignment mode, as long as it does not overlap with other address regions.
Peripheral and IO Base Address	–
UARTn Address Offset	–	Displays the base address when the Address Assignment Method is set to AUTO. When the Address Assignment Method is Manual, enter base address value. The wizard automatically rounds the value to 4 KB aligned addresses during IP generation. For example, 0x41230 is rounded to 0x41000.
SPIn Address Offset	–
I2Cn Address Offset	–
GPIOn Address Offset	–
User Timern Address Offset	–
APB3 Slave n Address Offset	–	Displays the base address when the Address Assignment Method is set to AUTO. When the Address Assignment Method is Manual, enter base address value. The wizard automatically rounds the value to APB sized aligned addresses during IP generation. For example, if the APB size is 64 KB, 0x23456 is rounded to 0x20000.
On-Chip RAM Base Address	–	Displays the base address. You cannot change it.

¹ RISC-V standard debug is supported starting from Efinity 2023.1 or later. Debugging with RISC-V standard debug is only supported by Efinity RISC-V Embedded Software IDE version 2023.1 or later.

² The RISC-V standard debug requires connecting the hard JTAG UPDATE and RESET signals. Before Efinity 2023.1, these signals were unconnected. However, with Efinity 2023.1, the generated example designs automatically connect both signals.