About the Example Design

This example targets Trion and Titanium development boards:

  • Trion® T120 BGA324 Development Board—The RTL design files are in the T120F324_devkit directory.
  • Titanium Ti60 F225 Development Board—The RTL design files are in the Ti60F225_devkit directory.
  • Titanium Ti180 J484 Development Board—The RTL design files are in the Ti180J484_devkit directory.
  • Topaz Tz170 J484 Development Board —The RTL design files are in the Tz170J484_devkit directory.
When you generate the IP core, the IP Manager creates the example design (PLL settings, SDC timing constraints, and I/O assignments) using the settings you chose in the wizard, with a few exceptions:
  • For the Trion board, the example design only supports external memory widths of 128 and 256 bits because the DDR controller only supports these widths. Therefore, do not choose 32 or 64 bits for the external memory.
  • The example design automatically connects UART0, SPI0, I2C0, GPIO0, the soft TAP pins, and the PLL source clock pins to top-level ports, and it assigns I/O pins to them (if they are enabled). If you add more of these peripherals, you need to connect them manually and create the I/O assignments for them.
  • The example design uses PLL settings that look for the best effort multiplier and divider values.
Note: The following description is for the example design using the default settings.

This example writes to and reads from the development board's memory module using the AXI interface:

  • For the Trion® T120 BGA324 Development Board, the design uses the board's LPDDR3 DRAM module.
  • For the Titanium Ti60 F225 Development Board, the design uses the board's HyperRAM module.
  • For the Titanium Ti180 J484 Development Board and Topaz Tz170 J484 Development Board , the design uses the board's LPDDR4/LPDDR4x DRAM module.

The Sapphire SoC is configured for:
  • 100 MHz frequency
  • External memory interface is enabled with a width of 128 and size of 3.5 GB
  • Caches are enabled with both Data Cache and Instruction Cache set to one way with cachesize of 4 KB
  • 4KB on-chip RAM size
  • Soft Debug Tap is disabled
  • UART 0 is enabled
  • SPI 0 is enabled
  • I2C 0 is enabled
  • GPIO 0 is enabled
  • APB3 0 is enabled
  • AXI4 Master is enabled
  • AXI Slave 0 is enabled
  • User interrupt A is enabled

Figure 1. Example Design Block Diagram
Table 1. Example Design Implementation
FPGA Logic + Adders Flipflops Multipliers
or DSP Blocks
 Memory Blocks fMAX (MHz) Language Efinity Version
T120 BGA324 C4 8,830 8,919 4 70 107 Verilog HDL 2023.1
Ti60 F225 C4 11,178 9,973 4 82 180 Verilog HDL 2023.1
Ti180 J484 C4 12,213 15,866 4 100 146 Verilog HDL 2023.1
Note: All example designs are constrained with a 100 MHz system clock.