Boot Sequence: Case B

The following figure shows the interaction of the FPGA and SPI flash during booting.

Figure 1. Boot Sequence Diagram

The boot sequence is:

  1. The PC starts at the system address 0xF900_0000 of the on-chip RAM and the PC jumps to 0xF900_0C00 for bootloader execution.
  2. The bootloader starts reading the SPI Flash address 0x0038_0000.
  3. The bootloader writes the user application to On-Chip RAM starting from system address 0xF900_0000.
  4. The bootloader finishes reading the user application from the SPI flash.
  5. The PC jumps to system address 0xF900_0000 and starts to execute the user application.
Note: For RISC-V SoC booting from a flash device, the GPIOs for the SPI signals (system_spi_*) should have the Register Option > register set in the Interface Designer. Refer to the IP Manager generated example design to see how you should set up the SPI channel.