Create a Custom AXI4 Master Peripheral

When you generate an example design for the Sapphire SoC, the IP Manager creates an example AXI4 peripheral and software code that you can use as a template to create your own peripheral. This example uses the simple dual-port RAM design to write to and read from the CPU through the AXI4 interface.

• Refer to the axi4_slave module in design_modules.v in the T120F324_devkit, Ti60F225_devkit, or Ti180J484_devkit directory for the RTL design.
• Refer to main.c in the embedded_sw/<SoC module>/software/standalone/axiDemo/src directory for the C code.