Modify the Bootloader

When you generate the Sapphire SoC, the IP Manager creates a pre-built bootloader .bin to target the on-chip RAM size you selected. If you assigned the peripheral addresses manually, you need to create a custom bootloader according to the following instructions.

Notice: You need the embedded software example code to make these changes; if you have not already done so, generate it.
Note: The pre-build bootloader binaries only use a single data line SPI. To utilize dual or quad data line SPI, refer to Modify the Bootloader Software to Enable Multi-Data Lines.

Modify the Bootloader Software to Extend the External Memory Size

First you need to modify the bootloader code:
  1. Open the bootloaderConfig.h file in the embedded_sw/<SoC module>/bsp/efinix/EfxSapphireSoc/app directory.
  2. Change the #define USER_SOFTWARE_SIZE parameter for the new on-chip RAM size and save.
  3. If you are using the MX25 flash device (e.g., Ti180J484 development kit), incorporate the following step into the bootloader application's makefile. Add CFLAGS+=-DMX25_FLASH before the line LDSCRIPT?=${BSP_PATH}linker/bootloader.Id
    Note: The addition of CFLAGS+=-DMX25_FLASH ensures that the necessary commands specific to the MX25 flash device are included in your build process.
  4. In Efinity RISC-V Embedded Software IDE, import standalone/bootloader project. Build the project to generate new bootloader.hex file.

Second, you update and re-generate the SoC in the IP Manager to point to your new bootloader.hex and change the application region size. The default maximum size is 124 KB.

  1. In the Sapphire IP wizard, go to the Cache/Memory tab.
  2. Turn on the Custom On-Chip RAM Application option.
  3. Click the Browse button for the user application path to select the new bootloader.hex you created in the previous set of steps.
  4. Generate the SoC.

Modify the Bootloader Software without External Memory Enabled

First, you need to modify the bootloader linker script:
  1. Open the bootloader.ld file in the embedded_sw/<SoC module>/bsp/efinix/EfxSapphireSoc/linker directory.
  2. Replace the MEMORY and PHDRS code with the following code. The <bootloader_address> should be 0xF9000000 + (<memory size>-1024), where <memory size> is your SoC's on-chip RAM size.
    MEMORY
{
    start (wxai!r) : ORIGIN = 0xF9000000, LENGTH = 512
    ram   (wxai!r) : ORIGIN = <bootloader_address>, LENGTH = 1024
}
                                
PHDRS
{
    start PT_LOAD;
    ram PT_LOAD;
}
Second you need to modify the bootloader code:
  1. Open the bootloaderConfig.h file in the embedded_sw/<SoC module>/bsp/efinix/EfxSapphireSoc/app directory.
  2. Change the #define USER_SOFTWARE_SIZE parameter for the new on-chip RAM size and save.
  3. If you are using the MX25 flash device (e.g., Ti180J484 development kit), incorporate the following step into the bootloader application's makefile. Add CFLAGS+=-DMX25_FLASH before the line LDSCRIPT?=${BSP_PATH}linker/bootloader.Id
    Note: The addition of CFLAGS+=-DMX25_FLASH ensures that the necessary commands specific to the MX25 flash device are included in your build process.
Note: If the new compiled bootloader does not fit into the allocated RAM, enable the following optimization in the makefile; DEBUG?=no, BENCH?=yes. Refer to Optimization Settings.

In Efinity RISC-V Embedded Software IDE, import standalone/bootloader project. Build the project to generate new bootloader.hex file.

Modify the Bootloader Software to Enable Multi-Data Lines

Before you can utilize the multi-data lines SPI in your bootloader, verify whether your board's flash drive supports Dual or Quad I/O modes.

In the Efinity RISC-V Embedded Software IDE example design, data ports 0 and 1 are exclusively connected. If you intend to use the Quad SPI for data transfer, you must establish connections for data ports 2 and 3. The following table shows the number of connected data lines interfacing with the respective FPGAs and flash devices.

Table 1. Multi-Data Lines Interface with FPGAs and Flash Devices
Development Kit Flash Device Number of Data Lines Connected
T8BGA81 W25Q80DLSNIG 2
T20BGA256 W25Q32JVSSIQ 2
T120BGA324 W25Q128JVSIQ 4
T120BGA576 W25Q128JVSIQ 4
Xyloni W25Q128JVSIM 2
Ti60F225 W25Q64JWSSIQ 2
Ti180J484/ Ti180M484/ Tz170J484 MX25U25645GZ4I00 4
In the bootloaderConfig.h file, you can define the configurations by selecting from the various data line modes:
  • SINGLE_SPI: Single data line
  • DUAL_SPI: Dual data line
  • QUAD_SPI: Quad data line

#define SINGLE_SPI 1 //define DUAL_SPI for dual data SPI or QUAD_SPI for quad data SPI

void bsp Main() { 
#ifndef SIM
        spiFlash_init(SPI, SPI_CS); 
        spiFlash_wake(SPI, SPI_CS); 
        spiFlash_exit4ByteAddr(SPI, SPI_CS);
#ifdef SINGLE_SPI
        spiFlash_f2m(SPI, SPI_CS, USER_SOFTWARE_FLASH, USER_SOFTWARE_MEMORY, USER_SOFTWARE_SIZE);
#elif DUAL_SPI
        spiFlash_f2m_dual(SPI, SPI_CS, USER_SOFTWARE_FLASH, USER_SOFTWARE_MEMORY,
        USER_SOFTWARE_SIZE); //dual data line half duplex 
#elif QUAD_SPI
        spiFlash_f2m_quad(SPI, SPI_CS, USER_SOFTWARE_FLASH, USER_SOFTWARE_MEMORY,
        USER_SOFTWARE_SIZE); //quad data line full duplex
#else
        #error "You must either define SINGLE_SPI to use single data line SPI, DUAL_SPI to use 
        dual data line SPI or QUAD_SPI to use quad data line SPI."
#endif 
#endif
        void (*userMain)() = (void (*)())USER_SOFTWARE_MEMORY; 
    #ifdef SMP
        smp_unlock(userMain); 
    #endif
        userMain();
}
Note: If the flash device is MX25 (from Ti180J484 development kit), add CFLAGS+=-DMX25_FLASH before the LDSCRIPT?=${BSP_PATH}linker/bootloader.Id into the bootloader application's makefile. Defining the MX25 includes the required commands specific to the MX25 flash device.