Enable Concurrent Debugging

About this task

To use concurrent debugging, follow these steps:
  1. On the Debug tab, turn on the Co-Debug option in efx_soc IP configuration.
  2. In the Efinity Debug Wizard, set up the signals and compile the project.
  3. Open the Debugger and turn on the Shared option.
  4. Launch the RISC-V Embedded Software IDE and import the target project.
  5. Right-click on group.launch and select on Run/Debug.
  6. Use the Debugger to perform the RTL debugging.
You can use both debugging processes at the same time; they do not interfere with each other.
Note: Co-debug only works with the FPGAs JTAG User TAP interface. When you turn on Co-Debug, the Soft Debug Tap option is hidden. Conversely, when you turn on Soft Debug Tap, the Co-Debug option is hidden.
Figure 1. Enable Co-Debug in IP Configuration (Step 1)

Figure 2. Enable Shared Debugging in Efinity Debugger (Step 3)
Figure 3. Co-Debug Launch Configurations Generated Automatically (Step 4)

Figure 4. Run/Debug via Co-Debug Flow (Step 5)
Important: You should always start RISC-V debugging first, and then RTL debugging. If you do RTL debugging first, the openOCD connection will close. If this happens, re-connect the Debugger.

Figure 5. Error when Debugging in Wrong Order and Reconnecting the Debugger