Efinix, Inc.
  • Install Software and SoC
    • Install the Efinity Software
    • Install the Efinity RISC-V Embedded Software IDE
  • IP Manager
    • Customizing the Sapphire SoC
    • SoC Configuration Guideline
    • Modify the Bootloader
      • Updating Bootloader with Efinity BRAM Initial Content Updater
  • Program the Board with the Sapphire RTL Design
    • About the Example Design
    • Enable the On-Board 10 MHz Oscillator (T120 BGA324 Board)
    • Enable the LPDDR4x Memory (Ti180 J484 Board)
    • Installing USB Drivers
    • Program the Development Board
  • Simulate
  • Launch Efinity RISC-V Embedded Software IDE
    • Sapphire SoC IDE Backward Compatibility
    • Launching the Efinity RISC-V Embedded Software IDE
    • IDE Launcher from Efinity
    • Optimization Settings
  • Create, Import, and Build a Software Project
    • Create a New Project
    • Import Sample Projects
    • Build
  • Debug with the OpenOCD Debugger
    • Launch the Debug Script
    • Debug
    • Debug - Multiple Cores
      • Debug - Single Core
      • Debug - SMP
    • Debug - Daisy Chain
    • Peripheral Register View
    • CSR Register View
    • FreeRTOS View
    • QEMU Emulator
  • Concurrent Debugging
    • Enable Concurrent Debugging
    • Disable Concurrent Debugging
    • Concurrent Debugging with Multiple Devices
    • Semihosting with Concurrent Debugging
  • Boot Sequence
    • Boot Sequence: Case A
    • Boot Sequence: Case B
    • Boot Sequence: Case C
    • Booting Multiple Cores
  • Create Your Own RTL Design
    • Target another FPGA
    • Target another Efinix Board
    • Target Your Own Board
    • Create a Custom AXI4 Master Peripheral
    • Create a Custom APB3 Peripheral
    • Use another DDR DRAM Module (Trion Only)
    • Use the I2C Interface for DDR Calibration
    • Remove Unused Peripherals from the RTL Design
  • Create Your Own Software
    • Deploying an Application Binary
      • Boot from a Flash Device
      • Boot from the OpenOCD Debugger
      • Copy a User Binary to Flash (Efinity Programmer)
    • About the Board Specific Package
    • List of Restructured BSP Files
    • Address Map
    • Example Software
      • Axi4Demo Design
      • apb3Demo
      • clintTimerInterruptDemo
      • coremark
      • customInstructionDemo
      • dCacheFlushDemo
      • dhrystone Example
      • FreeRTOS Examples
      • fpuDemo
      • gpioDemo
      • iCacheFlushDemo
      • inlineAsmDemo
      • i2cDemo Example
      • i2cEepromDemo
      • i2cMasterDemo Design
      • i2cMasterInterruptDemo Design
      • i2cSlaveDemo Design
      • memTest Example
      • nestedInterruptDemo
      • semihostingDemo
      • smpDemo
      • spiDemo Example
      • uartEchoDemo
      • UartInterruptDemo Example
      • userInterruptDemo Example
      • userTimerDemo
  • Third-party Debugger
  • Watchdog Timer
    • Introduction
    • Functional Description
    • Setting Limits for Both Counters
  • Using a UART Module
    • Using the On-board UART (Titanium)
    • Set Up a USB-to-UART Module (Trion)
    • Open a Terminal
    • Enable Telnet on Windows
  • Unified Printf
    • Bsp_print
    • Bsp_printf
    • Bsp_printf_full
    • Semihosting Printing
    • Preprocessor Directives
  • Using a Soft JTAG Core for Example Designs
    • Connect the FTDI Mini-Module
  • Migrating to the Sapphire SoC
    • Migrating to the Sapphire SoC v2.0 from a Previous Version
    • Migrating Ruby, Jade, and Opal to the Sapphire SoC
  • Troubleshooting
    • Error 0x80010135: Path too long (Windows)
    • Installation Error (2350): Path too long (Windows)
    • OpenOCD Error: timed out while waiting for target halted
    • Memory Test
    • OpenOCD error code (-1073741515)
    • OpenOCD Error: no device found
    • OpenOCD Error: failed to reset FTDI device: LIBUSB_ERROR_IO
    • OpenOCD Error: target 'fpga_spinal.cpu0' init failed
    • Eclipse Fails to Launch with Exit Code 13
    • Efinity Debugger Crashes when using OpenOCD
    • Exception in thread "main"
    • Unexpected CPUTAPID/JTAG Device ID
    • Non-existing file for the co_debug_register external tool
    • Error in Final Launch Sequence
    • Debug Core UUID Mismatch
    • Variable references empty selection: ${project_loc}
  • API Reference
    • Control and Status Registers
    • GPIO API Calls
    • I2C API Calls
    • I/O API Calls
    • Core Local Interrupt Timer API Calls
    • User Timer API Calls
    • PLIC API Calls
    • SPI API Calls
    • SPI Flash Memory API Calls
    • UART API Calls
    • RISC-V API Calls
    • Handling Interrupts
  • Inline Assembly
    • Introduction
    • Inline Assembly Syntax
      • Operands
    • RISC-V Registers

Debug with the OpenOCD Debugger

About this task

With the development board programmed and the software built, you are ready to configure the OpenOCD debugger and perform debugging. These instructions use the axiDemo example to explain the steps required.

  • Launch the Debug Script
  • Debug
  • Debug - Multiple Cores
  • Debug - Daisy Chain
  • Peripheral Register View
  • CSR Register View
  • FreeRTOS View
  • QEMU Emulator

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