Using a Soft JTAG Core for Example Designs

The Efinity® Debugger uses the hard JTAG TAP interface. Out of the box, the Sapphire SoC example design also uses the hard JTAG TAP interface for OpenOCD. If you try to use the same USB connection to the development board for both applications at the same time, they will conflict. To solve this problem, you use a soft JTAG block to handle the OpenOCD JTAG communication. With this method, you use an FTDI chip cable to connect the board to your computer (the Efinity® Debugger uses the USB cable).

The simplest way to implement a soft JTAG interface is to use the IP Manager to output an example design that enables the soft JTAG interface. The IP Manager automatically connects the soft JTAG pins to PMOD J12 when you turn on the Soft Debug Tap option.

Note: Efinix does not recommend the FTDI Chip C232HM-DDHSL-0 programming cable due to the possibility of the FPGA not being recognized or the potential for programming failures. You are encourage to use FTDI chip FT2232H or FT4232H mini-module.