Address Map

Because the address range might be updated, Efinix recommends that you always refer to the parameter name when referencing an address in firmware, not by the actual address. The parameter names and address mappings are defined in /embedded_sw/<module>/bsp/efinix/EfxSapphireSoc/include/soc.h.

Note: If you need to update the address map, use the IP Configuration wizard to change the addressing and then re-generate the SoC. Using this method keeps the software soc.h and FPGA netlist definitions aligned.
Table 1. Default Address Map, Interrupt ID, and Cached ChannelsThe AXI user master channel is in a cacheless region (I/O) for compatibility with AXI-Lite.
Device Parameter Size Interrupt ID Region
Off-chip memory SYSTEM_DDR_BMB 4 MB to 3.5 GB – Cache
GPIO 0 SYSTEM_GPIO_0_IO_CTRL 4 K [0]: 12
[1]: 13
 I/O
GPIO 1 SYSTEM_GPIO_1_IO_CTRL 4 K [0]: 14
[1]: 15
 I/O
I2C 0 SYSTEM_I2C_0_IO_CTRL 4 K 8 I/O
I2C 1 SYSTEM_I2C_1_IO_CTRL 4 K 9 I/O
I2C 2 SYSTEM_I2C_2_IO_CTRL 4 K 10 I/O
Core timer SYSTEM_CLINT_CTRL 4 K – I/O
PLIC SYSTEM_PLIC_CTRL 4 K – I/O
SPI master 0 SYSTEM_SPI_0_IO_CTRL 4 K 4 I/O
SPI master 1 SYSTEM_SPI_1_IO_CTRL 4 K 5 I/O
SPI master 2 SYSTEM_SPI_2_IO_CTRL 4 K 6 I/O
UART 0 SYSTEM_UART_0_IO_CTRL 4 K 1 I/O
UART 1 SYSTEM_UART_1_IO_CTRL 4 K 2 I/O
UART 2 SYSTEM_UART_2_IO_CTRL 4 K 3 I/O
User timer 0 SYSTEM_USER_TIMER_0_CTRL 4 K 19 I/O
User timer 1 SYSTEM_USER_TIMER_1_CTRL 4 K 20 I/O
User timer 2 SYSTEM_USER_TIMER_2_CTRL 4 K 21 I/O
User peripheral 0 IO_APB_SLAVE_0_CTRL 4 K to 1 MB – I/O
User peripheral 1 IO_APB_SLAVE_1_CTRL 4 K to 1 MB – I/O
User peripheral 2 IO_APB_SLAVE_2_CTRL 4 K to 1 MB – I/O
User peripheral 3 IO_APB_SLAVE_3_CTRL 4 K to 1 MB – I/O
User peripheral 4 IO_APB_SLAVE_4_CTRL 4 K to 1 MB – I/O
On-chip BRAM SYSTEM_RAM_A_BMB 1 - 512 KB – Cache
AXI user master SYSTEM_AXI_A_BMB 1 K to 256 MB – I/O
External interrupt – – [0]: 16
[1]: 17
[2]: 22
[3]: 23
[4]: 24
[5]: 25
[6]: 26
[7]: 27
 I/O
When accessing the addresses in the I/O region, type casting the pointer with the keyword volatile. The compiler recognizes this as a memory-mapped I/O register without optimizing the read/write access. An example of the casting is shown by the following command:
*((volatile u32*) address);

For the cached regions, the burst length is equivalent to an AXI burst length of 8. For the I/O region, the burst length is equivalent to an AXI burst length of 1. The AXI user master is compatible with AXI-Lite by disconnecting unused outputs and driving a constant 1 to the input port.

Note: The RISC-V GCC compiler does not support user address spaces starting at 0x0000_0000.

The following figure shows the default address map and the corresponding software parameters for modules in the memory space.

Figure 1. Sapphire Memory Space
Note: When external memory is disabled and auto address assignment is used, the AXI master is assigned to 0x0100_0000 to preserve the Sapphire memory space. However, you are allowed to set a desired base address in manual address assignment mode, as long as it does not overlap with other address regions.

The following figure shows the default address map and the corresponding software parameters for I/O.

Figure 2. Sapphire I/O Space