iCacheFlushDemo

This example (iCacheFlushDemo directory) illustrates how to invalidate the instruction cache. The instruction cache invalidation is critical to ensure the coherency between the cache and the main memory, ensuring that the CPU fetches the most up-to-date instructions. Firstly, the string funcA is copied into an array that is printed out in this example. The funcA can be seen as the output. Next, the string funcB is copied into the same array that is printed out again. Even though funcB is stored in the array, the funcA is seen as the output because the instruction cache has not yet been flushed.

To address this, the instruction cache invalidation is called upon. Once the instruction cache is invalidated, the funcB can be expected to be printed out in the UART console. Additionally, the most up-to-date instructions are fetched from the main memory.

By following this process, you can ensure that the CPU fetches the most recent instructions from the main memory and maintains coherency with the instruction cache. The design displays these messages in a UART terminal:

Expected 'funcA', Obtained : funcA
Expected 'funcA', Obtained : funcA
Expected 'funcB', Obtained : funcB
Test Complete