Titanium About the HyperRAM Interface

The HyperRAM has a density of 256 Mbits and a clock rate of up to 200 MHz. The HyperRAM supports double-data rates of up to 400 Mbps and supports a 16 bit data bus.

Figure 1. HyperRAM Block Diagram
Table 1. HyperRAM Signals (Interface to FPGA Fabric)
Signal Direction Description
CLK Input HyperRAM controller clock.
CLK90 Input 90 degree phase-shifted version of CLK.
CLKCAL Input Calibration clock for input data.
RST_N Input Active-low HyperRAM reset.
CS_N Input Active-low HyperRAM chip select signal.
CK_P_HI Input The clock provided to the HyperRAM. The clock is not required to be free-running. Registered in normal mode of DDIO.
CK_P_LO Input
CK_N_HI Input
CK_N_LO Input
RWDS_OUT_HI [1:0] Input Read/write data strobe input ports for data mask during write operation. Registered in normal mode/resync mode of DDIO.
RWDS_OUT_LO [1:0] Input
RWDS_OE [1:0] Input Read/write data strobe output enable port.
RWDS_IN_HI [1:0] Output Read/write data strobe output ports for latency indication, also center-aligned reference strobe for read data. Registered in normal mode/resync mode of DDIO.
RWDS_IN_LO [1:0] Output
DQ_OUT_HI [15:0] Input DQ input ports for command, address and data. Registered in normal mode of DDIO.
DQ_OUT_LO [15:0] Input
DQ_OE [15:0] Input DQ output enable port.
DQ_IN_HI [15:0] Output DQ output ports for data.
DQ_IN_LO [15:0] Output